Peripheral Interface: Difference between revisions
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Updated images and up to aligned DMA transfers
Mazamars312 (talk | contribs) (Domains data changed) |
Mazamars312 (talk | contribs) (Updated images and up to aligned DMA transfers) |
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=== PI Interface Process ===
Address output:
[[File:Rom address output.png|border|left|frameless|984x984px|Rom Address Output]]
Data Read:
[[File:Rom Read Data.png|alt=Rom Read Data|border|left|frameless|1003x1003px|Rom Read Data]]
Constant Read:
[[File:Constant ROM Access.png|border|left|frameless|1522x1522px|Constant ROM Access]]
=== Aligned DMA Transfer ===
An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit (2Byte) value as will transfer from that offset to RDRAM (more to come)
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