Peripheral Interface: Difference between revisions
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Domains data changed
Mazamars312 (talk | contribs) (Some PI data) |
Mazamars312 (talk | contribs) (Domains data changed) |
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Line 66:
|R/W
|This is a 8 bit counter for the timing on how long the Read or Write signal is to stay LOW before it can go HIGH
This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go
Default value set by games is (8'h12)
Line 77:
32'h0460_002C
|R/W
|This is a 8 bit counter for the timing on how many concurrent reads or writes can happen after 128 bytes of data are process and then the Cart bus has to advise to the Cart an update address.
Default value set by games is (8'h07)
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|PI_BSD_DOM1_RLS_REG
Line 86 ⟶ 88:
32'h0460_0030
|R/W
|This is a 8 bit counter for the timing on how long the Read or Write signal is to stay HIGH before it can go LOW
This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to idle or back to PI_BSD_DOMX_LAT_REG.
Default value set by games is (8'h03)
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