Peripheral Interface

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Parallel Interface Physical bus

The PI Bus is a Bi-directional and MUX'ed interface where there is a 16bit data path to the Rom, 64DD, Flash Ram and SRAM ram chips is used to send both the wanted address and data to and from the RCP. This is not to be confused with the serial EEPROM, CIC and RTC (real time clock) chips that go through the SI interface and PIF chip via the cartridge port as well.

Pin Name Cart pins Discription
AD0 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[16] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[0] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [0]

AD1 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[17] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[1] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [1]

AD2 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[18] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[2] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [2]

AD3 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[19] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[3] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [3]

AD4 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[20] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[4] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [4]

AD5 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[21] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[5] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [5]

AD6 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[22] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[6] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [6]

AD7 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[23] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[7] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [7]

AD8 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[24] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[8] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [8]

AD9 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[25] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[9] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [9]

AD10 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[26] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[10] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [10]

AD11 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[27] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[11] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [11]

AD12 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[28] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[12] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [12]

AD13 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[29] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[13] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [13]

AD14 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[30] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[14] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [14]

AD15 This data bit is used with the following signals to represent the following

/ALEH - Signal changes from HIGH to LOW: Address Bit[31] is latched internally in the ROM

/ALEL - Signal changes from HIGH to LOW: Address Bit[15] is latched internally in the ROM

/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [15]

/ALEH This internally latches the high address (Bits[31:16]) requested from the RCP in the rom when it goes from HIGH to LOW.

When this signal goes from LOW to HIGH it resets the internal address system so it can await for a new address request.

This stays HIGH when in idle and LOW when processing data.

/ALEL This internally latches the low address (Bits[15:0]) requested from the RCP in the rom when it goes from HIGH to LOW.

No action has been seen when this goes from LOW to HIGH.

This stays HIGH when in idle and LOW when processing data.

/WR This is the signal that sends a write command to the FLASH ram, SRAM or 64DD

When this signal goes from LOW to HIGH it the RCP will then send data (The ROM will go in to a High-z State to not affect the data bus) This will also increase the internal address counter in the FLASH/SRAM so the data is collected for the next cycle of the /WR signaling.

No action has been seen when this goes from HIGH to LOW. It will do the HIGH to LOW change when the domain latency (PI_BSD_DOMX_RLS_REG) counter has been reached and also then the PI_BSD_DOMX_RLS_REG counter.(More on this counters later)

This stays HIGH when in idle and LOW when processing write data.

/RD This is the signal that sends a read command to the ROM, FLASH ram, SRAM or 64DD.

When this signal goes from LOW to HIGH it the address selected rom/FLASH/SRAM/64DD will then send data. This will also increase the internal address counter in the ROM/FLASH/SRAM/64DD so the data is collected for the next cycle of the /RD signaling.

No action has been seen when this goes from HIGH to LOW. It will do the HIGH to LOW change when the domain latency (PI_BSD_DOMX_RLS_REG) counter has been reached and also then the PI_BSD_DOMX_RLS_REG counter. (More on this counters later)

This stays HIGH when in idle and LOW when processing Read data.

Parallel Interface Domains

Physical Address Range Domain Common Devices
0x0500 0000 -

0x05FF FFFF

2 64DD Control Regs
0x0600 0000 -

0x07FF FFFF

1 64DD Boot Rom
0x0800 0000 -

0x0FFF FFFF

2 Flash Ram (need to confirm)

SRAM normal location (need to confirm)

0x1000 0000 -

0x1FBF FFFF

1 Standard Game Cartridge location
0x1FD0 0000 -

0x7FFF FFFF

1

Parallel Interface Registers

0x0460 0000 to 0x046F FFFF  Address range:

Reg Name Reg Address (32Bit) Read or Write Discription
PI_DRAM_ADDR_REG [23:0] 32'h0460_0000 R/W This is the starting address in RDRAM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address
PI_CART_ADDR_REG [31:0] 32'h0460_0004 R/W This is the starting address in ROM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address
PI_RD_LEN_REG [23:0] 32'h0460_0008 R/W The is the amount of bytes to be transferred from RDRAM to the ROM location (this has to be a value in a multiple of 16bits (2 Bytes)).

This number is the total amount of bytes you want to transfer - 1

PI_WR_LEN_REG [23:0] 32'h0460_000C R/W The is the amount of bytes to be transferred from ROM to the RDRAM location (this can be byte amount but weird un-alignment issues happen. more on this later)

This number is the total amount of bytes you want to transfer - 1

PI_STATUS_REG 32'h0460_0010 R/W On Read:

Bit [0] : DMA is busy

Bit [1] : IO Busy

Bit [2] : DMA Error

Bit [3] : Interrupt (DMA Completed)

On Write:

Bit [0] : Reset the DMA controller and stop any transfer begin done

Bit [1] : Clear Interrupt

PI_BSD_DOM1_LAT_REG

PI_BSD_DOM2_LAT_REG [7:0]

32'h0460_0014

32'h0460_0024

R/W This is a 8 bit counter for the timing between sending the address to the ROM and when to read or write the block of data over the cart bus

This counter runs after the Low Address is asserted on the bus and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the bus can then start the Read or write process. Then the PI_BSD_DOMX_RLS_REG process starts for the data transfer

Default value set by games is (8'h40)

PI_BSD_DOM1_PWD_REG

PI_BSD_DOM2_PWD_REG

[7:0]

32'h0460_0018

32'h0460_0028

R/W This is a 8 bit counter for the timing on how long the Read or Write signal is to stay LOW before it can go HIGH. Once the Read signal goes high Data on the bus from the rom is read to the N64. The same is with the Write signal but the RCP outputs the data

This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to PI_BSD_DOM1_RLS_REG.

Default value set by games is (8'h12)

PI_BSD_DOM1_PGS_REG

PI_BSD_DOM2_PGS_REG

[7:0]

32'h0460_001C

32'h0460_002C

R/W This is a 8 bit counter for the timing on how many concurrent reads or writes can happen after 128 bytes of data are process and then the Cart bus has to advise to the Cart an update address.

Default value set by games is (8'h07)

PI_BSD_DOM1_RLS_REG

PI_BSD_DOM2_RLS_REG

[7:0]

32'h0460_0020

32'h0460_0030

R/W This is a 8 bit counter for the timing on how long the Read or Write signal is to stay HIGH before it can go LOW.

This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to idle or back to PI_BSD_DOMX_LAT_REG.

Default value set by games is (8'h03)

PI Interface Process

Address output:
Rom Address Output



Data Read:
Rom Read Data



Constant Read:
Constant ROM Access




Aligned DMA Transfer

An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit (2Byte) value as will transfer from that offset to RDRAM.

The PI_RD_LEN_REG and PI_WR_LEN_REG can be any length, as long as it is a 2 byte aligned amount (more testing is to be done on this to confirm this)

Unaligned DMA transfer

An un-aligned ROM dma transfer is when you use the PI_DRAM_ADDR_REG and not set it as a 8 Byte aligned address and use variable PI_RD_LEN_REG and PI_WR_LEN_REG lengths.

The following rules are based on assumptions via the created test ROMs by Krom, Mazamars312 and Lemmy (https://github.com/PeterLemon/N64/tree/master/CPUTest/DMAAlignment-PI-cart)

This are example DMA transfers
RDRAM Address ROM Address Read or Write Length What happens
0000_0100 1000_1000 Read 0x7F (128 Bytes) This is a normal aligned transfer
0000_0102 1000_1000 Read 0x7F (128 Bytes) The start of the ROM data is transferred to RDRAM offset as expected (So the first two bytes of RDRAM are not affected by this write).

However, this is where we see that the last 2 bytes are dropped from the transfer. Thus only making it a 0x7D length transfer (126 bytes - 1)

0000_0106 1000_1000 Read 0x7F (128 Bytes) The start of the ROM data is transferred to RDRAM offset as expected (So the first 6 bytes of RDRAM are not affected by this write).

However, this is where we see that the last 6 bytes are dropped from the transfer. Thus only making it a 0x79 length transfer (122 bytes - 1)

0000_0106 1000_1000 Read 0x17 (24 Bytes) The start of the ROM data is transferred to RDRAM offset as expected (So the first 6 bytes of RDRAM are not affected by this write).

However, this is where we see that the last 6 bytes are dropped from the transfer. Thus only making it a 0x11 length transfer (18 bytes - 1)

0000_0106 1000_1000 Read 0xFF (256 Bytes) This is where we have found that internally the N64 can only DMA blocks of 128 at a time to and from RDRAM as a burst to the PI controller.

The First 128 Bytes:

The start of the ROM data is transferred to RDRAM offset as expected (So the first two bytes of RDRAM are not affected by this write).

However, this is where we see that the last 6 bytes are dropped from the transfer. Thus only making it a 0x79 length transfer (122 bytes - 1)

The Second 128 Bytes:

This will do a normal Aligned DMA transfer from the RDRAM offset 128 to 255. From this we believe the first DMA transfer is corrupted due to some internal issue with the PI controller and the RDRAM controller.

The image blow shows this example (look at address 112 -> 127) this shows the last 6 Bytes are not transferred. (Confirmed by Krom)
DMA UnAligned 6byte Offset.png
0000_0106 1000_1000 Write 0x7F (128 Bytes) *** Writes to Flash and SRAM to be tested ***