RDRAM Interface: Revision history

12 December 2023

• curprev 12:2612:26, 12 December 2023‎ Rasky talk contribs‎ 29,963 bytes +7,181‎ →‎Memory addressing Tag: Visual edit

5 November 2023

• curprev 13:4513:45, 5 November 2023‎ Phire talk contribs‎ 22,782 bytes +1,135‎ Document Count mapping Tag: Visual edit
• curprev 13:1913:19, 5 November 2023‎ Phire talk contribs‎ 21,647 bytes +523‎ RI_LATENCY speculation Tag: Visual edit: Switched
• curprev 13:0913:09, 5 November 2023‎ Phire talk contribs‎ 21,124 bytes +2,542‎ Better explanation about bank status tracking, and why RAM is limited to 8MiB Tag: Visual edit

4 November 2023

• curprev 02:2502:25, 4 November 2023‎ Tharo talk contribs‎ 18,582 bytes +74‎ RI_REFRESH: Emphasize that "refresh enable" refers specifically to the automatic refresh issued on VI HSYNC, other small tweaks.
• curprev 00:4900:49, 4 November 2023‎ Tharo talk contribs‎ 18,508 bytes +1,386‎ RI_SELECT: Partial research into the set of allowed configurations

3 November 2023

• curprev 22:0322:03, 3 November 2023‎ Tharo talk contribs‎ 17,122 bytes +607‎ RI_CONFIG and RI_CURRENT_LOAD: Relate fields to relevant RAC signals, document read behavior for RI_CURRENT_LOAD
• curprev 21:1221:12, 3 November 2023‎ Tharo talk contribs‎ 16,515 bytes +125‎ RI_ERROR: Mention that even if the OverRange error is flagged it does not inhibit RDRAM packets from being sent out
• curprev 19:0319:03, 3 November 2023‎ Tharo talk contribs‎ 16,390 bytes +586‎ RI_BANK_STATUS: Further details
• curprev 05:5905:59, 3 November 2023‎ Tharo talk contribs‎ m 15,804 bytes +33‎ RI_REFRESH: MultiBank bitfield width is four bits. Tag: Visual edit: Switched
• curprev 05:4505:45, 3 November 2023‎ Phire talk contribs‎ 15,771 bytes +51‎ No idea what DmaLatencyOverlap does, but we do know it's 4 bits. Tag: Visual edit: Switched
• curprev 05:3405:34, 3 November 2023‎ Phire talk contribs‎ 15,720 bytes +238‎ More RI_ERROR research. Fix formatting errors. Tag: Visual edit: Switched
• curprev 05:1705:17, 3 November 2023‎ Phire talk contribs‎ 15,482 bytes +2,262‎ Fill in RI_ERROR and RI_BANK_STATUS Tag: Visual edit: Switched

27 October 2023

• curprev 07:1907:19, 27 October 2023‎ Phire talk contribs‎ 13,220 bytes +732‎ Add details about refresh timings Tag: Visual edit: Switched

13 July 2023

• curprev 11:1011:10, 13 July 2023‎ Rasky talk contribs‎ 12,488 bytes +429‎ →‎Memory addressing Tag: Visual edit

24 February 2023

• curprev 02:5702:57, 24 February 2023‎ Lidnariq talk contribs‎ 12,059 bytes +80‎ don't imply that whatever this permits more than 8MiB of RAM to the CPU

14 December 2022

• curprev 22:5622:56, 14 December 2022‎ Bsmiles32 talk contribs‎ m 11,979 bytes −38‎ Undo revision 4627 by Bsmiles32 (talk) Tag: Undo
• curprev 22:5522:55, 14 December 2022‎ Bsmiles32 talk contribs‎ 12,017 bytes +38‎ →‎Registers
• curprev 22:4222:42, 14 December 2022‎ Bsmiles32 talk contribs‎ 11,979 bytes +844‎ Add placeholder for RI_LATENCY
• curprev 22:3322:33, 14 December 2022‎ Bsmiles32 talk contribs‎ 11,135 bytes +225‎ Add reference to N64 patent
• curprev 22:2322:23, 14 December 2022‎ Bsmiles32 talk contribs‎ 10,910 bytes +1,357‎ Add RI_REFRESH description

12 December 2022

• curprev 23:0923:09, 12 December 2022‎ Bsmiles32 talk contribs‎ 9,553 bytes −5‎ →‎0x0470 000C - RI_SELECT
• curprev 23:0423:04, 12 December 2022‎ Bsmiles32 talk contribs‎ 9,558 bytes +1,116‎ Add RI_SELECT description

2 September 2021

• curprev 00:4900:49, 2 September 2021‎ Bigbass talk contribs‎ m 8,442 bytes +104‎ Fixed header and minor formatting. Added SMode packet source.
• curprev 00:4200:42, 2 September 2021‎ Bigbass talk contribs‎ 8,338 bytes +66‎ Cleaned formatting and added content to RI_MODE register.

1 September 2021

• curprev 23:3623:36, 1 September 2021‎ Bigbass talk contribs‎ 8,272 bytes +363‎ Verified the RI contains a RAC, and clarified which specific registers were defined on this page.

31 August 2021

• curprev 23:4323:43, 31 August 2021‎ Bsmiles32 talk contribs‎ m 7,909 bytes −35‎ No edit summary Tag: Visual edit
• curprev 22:1522:15, 31 August 2021‎ Bsmiles32 talk contribs‎ 7,944 bytes −36‎ Clarify RI_CONFIG and RI_CURRENT_LOAD with newly found RAC datasheet Tag: Visual edit
• curprev 22:0022:00, 31 August 2021‎ Bsmiles32 talk contribs‎ 7,980 bytes +424‎ Add link to some RAC datasheet Tag: Visual edit
• curprev 21:0821:08, 31 August 2021‎ Bsmiles32 talk contribs‎ 7,556 bytes +448‎ RI translation does very likely "disable" address swapping for registers operations by duplicating content between Adr[28:20] and Adr[19:11] Tag: Visual edit

30 August 2021

• curprev 22:4422:44, 30 August 2021‎ Bsmiles32 talk contribs‎ m 7,108 bytes −3‎ bullet formatting Tag: Visual edit
• curprev 22:4322:43, 30 August 2021‎ Bsmiles32 talk contribs‎ 7,111 bytes −1,286‎ RDRAM IdMatch procedure explanation has moved to RDRAM page Tag: Visual edit

29 August 2021

• curprev 22:1722:17, 29 August 2021‎ Bsmiles32 talk contribs‎ 8,397 bytes +3,547‎ Tentative description of RDRAM address mapping Tag: Visual edit
• curprev 14:5914:59, 29 August 2021‎ Bsmiles32 talk contribs‎ 4,850 bytes +1,018‎ Add RI_CURRENT_LOAD description
• curprev 14:5314:53, 29 August 2021‎ Bsmiles32 talk contribs‎ m 3,832 bytes +5‎ No edit summary Tag: Visual edit
• curprev 14:2514:25, 29 August 2021‎ Bsmiles32 talk contribs‎ 3,827 bytes +1,337‎ Add RI_CONFIG register description. Tag: Visual edit: Switched
• curprev 13:0313:03, 29 August 2021‎ Bsmiles32 talk contribs‎ 2,490 bytes +1,761‎ No edit summary Tag: Visual edit: Switched
• curprev 12:1012:10, 29 August 2021‎ Bsmiles32 talk contribs‎ 729 bytes +729‎ Small intro for RDRAM Interface Tag: Visual edit