RDRAM Interface

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The RDRAM Interface (or RI) act as a controller of the RDRAM channel to which one or more RDRAM modules are connected. It converts memory accesses from the system into RDRAM protocol commands, to which RDRAM modules responds. The RI very likely integrates a RDRAM ASIC Cell (or RAC) in order to take care of the low level details of the RDRAM bus. Further details about such a RAC can be found in datasheets like this one (even if it may not be the very same version used in the official RI).

The memory area devoted to RDRAM Interface and RDRAM modules is divided as follow :

memory area devoted to RDRAM Interface and modules
Address Range Name Description
0x0000 0000 0x03EF FFFF RDRAM memory Allows to access RDRAM memory of configured module
0x03F0 0000 0x03FF FFFF RDRAM registers Allows to access RDRAM register of configured module
0x0470 0000 0x047F FFFF RI registers Allows to configure RDRAM Interface behavior

Registers

0x0470 0000 - RI_MODE

RI_MODE 0x0470 0000
31:24 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
23:16 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
15:8 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
7:0 U-? U-? U-? U-? RW-? RW-? RW-? RW-?
— — — — Stop_R Stop_T Op_Mode [1:0] 
READ/WRITE:
    [3]    Enable/Disable controller Receive clock automatic stopping.
    [2]    Enable/Disable controller Transmit clock automatic stopping.
    [1:0]  Operating mode of RDRAM modules (not sure if it is the operating mode of the controller, if it makes the controller forward orders to place RDRAM modules in these states).
           0: Reset. place device in known state after poweron.
           1: Active. device is active and ready to receive requests. This mode consumes the most power and is not used directly.
           2: Standby. device automatically transition to this state after servicing a transaction. This is the default operating mode.
           NOTE: some RDRAM datasheets mention a 4th mode PowerDown, but I'm not sure it is supported in N64 configuration.
           NOTE: transition between these states takes several cycles, so after setting them some delay is necessary for them to be effective.


0x0470 0004 - RI_CONFIG

RI_CONFIG 0x0470 0004
31:24 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
23:16 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
15:8 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
7:0 U-? RW-? RW-? RW-? RW-? RW-? RW-? RW-?
— AutoCC CC [5:0] 
READ?/WRITE:
    [6]      Enable/Disable automatic current calibration from controller.
             It selects whether the the value CC[5:0] will be written to current control register (AutoCC=0), or an internally generated value (AutoCC=1).
    [5:0]    Current Control Input. The value to be loaded into current control register when autoCC is disabled.


0x0470 0008 - RI_CURRENT_LOAD

RI_CURRENT_LOAD 0x0470 0008
31:24 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
23:16 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
15:8 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — —
7:0 U-? U-? U-? U-? U-? U-? U-? U-?
— — — — — — — — 
WRITE:
     TOVERIFY: Any write to this register will load a new value into the current control register. The value loaded depends on the value of AutoCC. See RI_CONFIG for details.
     TOVERIFY: When AutoCC=1, a sufficient delay should be observed to let CC autocalibration stabilize.

...

TODO: remaining registers

Memory addressing

RI translate memory accesses in the range 0x0000 0000 - 0x03FF FFFF into suitable RDRAM protocol packets with proper command type and 36 bit address. See RDRAM addressing paragraph for details about how 36bit addresses are interpreted.

Address conversion done by RI (TOVERIFY):

Address Range Adr[35:29] Adr[28:20] Adr[19:11] Adr[10:0] BCastRWrite Description
0x0000 0000 0x03EF FFFF 0 (address >> 20) & 0x3F (address >> 11) & 0x1FF address & 0x7FF 0 Memory-space access
0x03F0 0000 0x03F7 FFFF 0 (address >> 10) & 0x1FF (address >> 10) & 0x1FF address & 0x3FF (address >> 19) & 0x1 == 0 Register-space access
0x03F8 0000 0x03FF FFFF 0 (address >> 10) & 0x1FF (address >> 10) & 0x1FF address & 0x3FF (address >> 19) & 0x1 == 1 Broadcast register write


Examples :

Assuming a standard RDRAM configuration of 4x2x9Mbit RDRAM each with IdField = 2*k for module k = 0..3 and SwapField = 0 for all modules (eg. no address swapping, Adr = AdrS).

  • Reading at address 0x003A BCDE, gives the following Adr[35:20] = 3, Adr[19:0] = 0xABCDE, BCastRWrite = 0. Since we have 2x9Mbit modules, Adr[20] is ignored for Id matching and therefore RDRAM with IdField == 2 gives a match. This means RDRAM module 1 will be read at address 0x1ABCDE.
  • Writing at address 0x03F0 0808, gives Adr[35:20] = 2, Adr[19:0] = 8, BCastRWrite = 0. Which means writing to RDRAM module 1 delay register.
  • Writing at address 0x03F8 0008, gives BCastRWrite = 1, Adr[19:0] = 8. Which means broadcast writing to all RDRAM modules delay registers.

Remarks :

  • Early version of RCP reserved fewer bits for RDRAM register address (eg. Adr[35:20] = (address >> 9) & 0x3FF; Adr[19:0] = address & 0x1FF) which didn't allow to access RDRAM register 128 (Row register) which is at offset 0x200.
  • The presented address map supports up to 32x 2x9Mbit RDRAM modules.
  • Standard DRAM initialization only supports up to 8 modules, but can mix 2x9Mbit and 1x9Mbit modules. In that case, 2x9Mbit modules are placed before 1x9Mbit modules.
  • Standard DRAM initialization procedure, doesn't make use of address swapping feature, even though it may increase DRAM hit rate according to datasheets.
  • Register-space addresses duplicates the content between Adr[28:20] and Adr[19:11] to not be affected by RDRAM address swapping features. Indeed, whereas address swapping is desirable for RDRAM memory to benefit from row internal row caching, registers won't benefit from the swapping and would complicate usage of registers in such a case.
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