Reality Signal Processor/CPU Core: Difference between revisions
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Reality Signal Processor/CPU Core (view source)
Revision as of 04:54, 24 September 2023
, 9 months agoA few value corrections
Spacebeans (talk | contribs) m (A few value corrections) |
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!Description
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|<code>vlt</code>
|Select the lower value between two VPR
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|<code>veq</code>
|Compare two VPR to check if they are equal
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|<code>vne</code>
|Compare two VPR to check if they are different
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|<code>vge</code>
|Select the greater or equal value between two VPR
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|<code>vcl</code>
|Clip a VPR against two bounds (lower 16-bits)
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|<code>vch</code>
|Clip a VPR against two bounds (higher 16-bits)
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|<code>vcr</code>
|Clip a VPR against a pow-2 bound
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|<code>vmrg</code>
|Merge two VPR selecting each lane according to flags
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<code>mtc2</code> moves the lower 16 bits of the general purpose register <code>rt</code> to the bytes <code>VS[vs_elem+1..vs_elem]</code>. If <code>vs_elem</code> is 15, only <code>VS[vs_elem]</code> is written (with <code>rt[15..8]</code>).
<code>mfc2</code> moves the 2 bytes <code>VS[vs_elem+1..vs_elem]</code> to GPR <code>rt</code>, sign extending the 16 bits value to
<code>ctc2</code> moves the lower 16 bits of GPR <code>rt</code> into the control register specified by <code>vs</code>, while <code>cfc2</code> does the reverse, moving the control register specified by <code>vs</code> into GPR <code>rt</code>, sign extending to
{| class="wikitable"
!<code>vs</code>
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