RDRAM Interface: Difference between revisions
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don't imply that whatever this permits more than 8MiB of RAM to the CPU
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(don't imply that whatever this permits more than 8MiB of RAM to the CPU) |
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* Early version of RCP reserved fewer bits for RDRAM register address (eg. Adr[35:20] = (address >> 9) & 0x3FF; Adr[19:0] = address & 0x1FF) which didn't allow to access RDRAM register 128 (Row register) which is at offset 0x200.
* The presented address map supports up to 32x 2x9Mbit RDRAM modules. However, a maximum of 8MiB is accessible with the IPL3 in all commercial carts.
* Standard DRAM initialization only supports up to 8 modules, but can mix 2x9Mbit and 1x9Mbit modules. In that case, 2x9Mbit modules are placed before 1x9Mbit modules.
* Standard DRAM initialization procedure, doesn't make use of address swapping feature, even though it may increase DRAM hit rate according to datasheets.
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