Reality Signal Processor/CPU Core: Difference between revisions
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→128-bit vector loads: LQV, LRV
Line 735:
</syntaxhighlight>Notice that the element field is optional (defaults to 0) and is usually not specified because these instructions are meant to affect the whole vector. The element field can be specified using the lane syntax (<code>e(N)</code>) or a raw number which maps to the byte offset inside the vector.
===== Pseudo-code =====
<syntaxhighlight lang="c">
// lqv
addr = GPR[base] + (offset * 16)
end = addr | 15
size = MIN(end-addr, 15-element)
VPR[vt][element..element+size] = DMEM[addr..addr+size]
</syntaxhighlight><syntaxhighlight lang="c">
// lrv
end = GPR[base] + (offset * 16)
addr = end & ~16
size = MIN(end-addr, 15-element)
VPR[vt][element..addr+size] = DMEM[addr..addr+size]
</syntaxhighlight>
===== Description =====
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