Peripheral Interface: Difference between revisions
Jump to navigation
Jump to search
More on the Unaligned DMA process
Mazamars312 (talk | contribs) (Update to the phy details of the PI interface) |
Mazamars312 (talk | contribs) (More on the Unaligned DMA process) |
||
Line 239:
|32'h0460_0008
|R/W
|The is the amount of bytes to be transferred from RDRAM to the ROM location (this has to be a value in a multiple of 16bits (2 Bytes)).
This number is the total amount of bytes you want to transfer - 1
|-
|PI_WR_LEN_REG [23:0]
|32'h0460_000C
|R/W
|The is the amount of bytes to be transferred from ROM to the RDRAM location (this can be byte amount but weird un-alignment issues happen. more on this later)
This number is the total amount of bytes you want to transfer - 1
|-
|PI_STATUS_REG
Line 336 ⟶ 338:
===Aligned DMA Transfer===
An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit (2Byte) value as will transfer from that offset to RDRAM
The PI_RD_LEN_REG and PI_WR_LEN_REG can be any length, as long as it is a 2 byte aligned amount (more testing is to be done on this to confirm this)
=== Unaligned DMA transfer ===
An un-aligned ROM dma transfer is when you use the PI_DRAM_ADDR_REG and not set it as a 8 Byte aligned address and use variable PI_RD_LEN_REG and PI_WR_LEN_REG lengths.
The following rules are based on assumptions via the created test ROMs by Krom, Mazamars312 and Lemmy ([https://github.com/PeterLemon/N64/tree/master/CPUTest/DMAAlignment-PI-cart https://github.com/PeterLemon/N64/tree/master/CPUTest/DMAAlignment-PI-cart)]
{| class="wikitable"
|+This are example DMA transfers
!RDRAM Address
!ROM Address
!Read or Write
!Length
!What happens
|-
|0000_0100
|1000_1000
|Read
|0x7F (128 Bytes)
|This is a normal aligned transfer
|-
|0000_0102
|1000_1000
|Read
|0x7F (128 Bytes)
|The start of the ROM data is transferred to RDRAM offset as expected (So the first two bytes of RDRAM are not affected by this write).
However, this is where we see that the last 2 bytes are dropped from the transfer. Thus only making it a 0x7D length transfer (126 bytes - 1)
|-
|0000_0106
|1000_1000
|Read
|0x7F (128 Bytes)
|The start of the ROM data is transferred to RDRAM offset as expected (So the first 6 bytes of RDRAM are not affected by this write).
However, this is where we see that the last 6 bytes are dropped from the transfer. Thus only making it a 0x79 length transfer (122 bytes - 1)
|-
|0000_0106
|1000_1000
|Read
|0x17 (24 Bytes)
|The start of the ROM data is transferred to RDRAM offset as expected (So the first 6 bytes of RDRAM are not affected by this write).
However, this is where we see that the last 6 bytes are dropped from the transfer. Thus only making it a 0x11 length transfer (18 bytes - 1)
|-
|0000_0106
|1000_1000
|Read
|0xFF (256 Bytes)
|This is where we have found that internally the N64 can only DMA blocks of 128 at a time to and from RDRAM as a burst to the PI controller.
The First 128 Bytes:
The start of the ROM data is transferred to RDRAM offset as expected (So the first two bytes of RDRAM are not affected by this write).
However, this is where we see that the last 6 bytes are dropped from the transfer. Thus only making it a 0x79 length transfer (122 bytes - 1)
The Second 128 Bytes:
This will do a normal Aligned DMA transfer from the RDRAM offset 128 to 255. From this we believe the first DMA transfer is corrupted due to some internal issue with the PI controller and the RDRAM controller.
The image blow shows this example (look at address 112 -> 127) this shows the last 6 Bytes are not transferred. (Confirmed by Krom)[[File:DMA UnAligned 6byte Offset.png|center|thumb|300x300px]]
|-
|0000_0106
|1000_1000
|Write
|0x7F (128 Bytes)
|*** Writes to Flash and SRAM to be tested ***
|}
| |||