N64brew Wiki

Peripheral Interface: Difference between revisions

Page Discussion

Peripheral Interface (view source)

Revision as of 02:29, 17 November 2022

5,980 bytes added ,  1 year ago
reformat PI registers
VisualWikitext
(Remove section that is replaced by longer text about the PI bus)
(reformat PI registers)
Line 82:
| colspan="8" | DRAM_ADDR[15:8]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RWR-0
|-
| colspan="8" | DRAM_ADDR[7:0]
Line 88:
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | DRAM_ADDR[23:0] | RDRAMStart address used in RDRAM for PI DMAs; lsbit is always 0
}}
 
Note that DMA transfers are buggy if the three lsbits are not all zero, see [[#Unaligned DMA transfer|below]].
 
==== <span style="display:none;">0x0460 0004 - PI_CART_ADDR ====
----
{{#invoke:Register table|head|550px|PI_CART_ADDR <code>0x0460 0004</code>}}
{{#invoke:Register table|row|31:24}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | CART_ADDR[31:24]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | CART_ADDR[23:16]
{{#invoke:Register table|row|15:8}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | CART_ADDR[15:8]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || R-0
|-
| colspan="8" | CART_ADDR[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-0 | CART_ADDR[31:0] | Start address in cartridge for PI DMAs; lsbit is always 0
}}
 
==== <span style="display:none;">0x0460 0008 - PI_RD_LEN ====
----
{{#invoke:Register table|head|550px|PI_RD_LEN <code>0x0460 0008</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | RD_LEN[23:16]
{{#invoke:Register table|row|15:8}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | RD_LEN[15:8]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || ???
|-
| colspan="8" | RD_LEN[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | RD_LEN[23:0] | Number of bytes, -1, to be transferred from cart; lsbit must always be 1 (but does it exist? what goes wrong if it isn't?)
}}
 
==== <span style="display:none;">0x0460 000C - PI_WR_LEN ====
----
{{#invoke:Register table|head|550px|PI_WR_LEN <code>0x0460 000C</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | WR_LEN[23:16]
{{#invoke:Register table|row|15:8}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | WR_LEN[15:8]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || ???
|-
| colspan="8" | WR_LEN[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | WR_LEN[23:0] | Number of bytes, -1, to be transferred to cart; lsbit must always be 1, and undocumented things go wrong if it is not
}}
 
==== <span style="display:none;">0x0460 0010 - PI_STATUS ====
----
{{#invoke:Register table|head|550px|PI_STATUS <code>0x0460 0010</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-0 || U-0 || U-0 || U-0 || R-0 || R-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4"|Details below
{{#invoke:Register table|foot}}
<pre>
READ: WRITE:
[3] Interrupt (DMA completed) [3] -
[2] DMA error [2] -
[1] I/O busy [1] Clear Interrupt
[0] DMA is busy [0] Reset DMA controller and stop any transfer being done
</pre>
 
==== <span style="display:none;">0x0460 00n4 - PI_BSD_DOMn_LAT ====
----
{{#invoke:Register table|head|550px|PI_BSD_DOM1_LAT <code>0x0460 0014</code><br>
PI_BSD_DOM2_LAT <code>0x0460 0024</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | BSD_DOMn_LAT[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-8 | Undefined | Initialized to <code>0</code>
| 7-0 | PI_BSD_DOMn_LAT[7:0] | The "LATch" time is the number of FSB cycles, -1, after the address has been sent (a falling edge of ALEL) before the first read or write may start
}}
 
The default value for PI_BSD_DOM1_LAT is 0x40 meaning (0x40+1)·16 = 1040ns, copied by IPL2 from the cartridge header.
 
==== <span style="display:none;">0x0460 00n8 - PI_BSD_DOMn_PWD ====
----
{{#invoke:Register table|head|550px|PI_BSD_DOM1_PWD <code>0x0460 0018</code><br>
PI_BSD_DOM2_PWD <code>0x0460 0028</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | BSD_DOMn_PWD[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-8 | Undefined | Initialized to <code>0</code>
| 7-0 | PI_BSD_DOMn_PWD[7:0] | The "Pulse WiDth" is the number of FSB cycles, -1, the read or write signals are held low
}}
 
The default value for PI_BSD_DOM1_PWD is 0x12 meaning (0x12+1)·16 = 304ns, copied by IPL2 from the cartridge header.
 
==== <span style="display:none;">0x0460 00nC - PI_BSD_DOMn_PGS ====
----
{{#invoke:Register table|head|550px|PI_BSD_DOM1_PGS <code>0x0460 001C</code><br>
PI_BSD_DOM2_PGS <code>0x0460 002C</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | BSD_DOMn_PGS[3:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-4 | Undefined | Initialized to <code>0</code>
| 3-0 | PI_BSD_DOMn_PGS[3:0] | The "PaGe Size" is the number of bits, -1, of automatic incrementing behavior supported by the cartridge hardware.
}}
 
The default value for PI_BSD_DOM1_PGS is 0x7, copied by IPL2 from the cartridge header. This means the PI assumes it can transfer at most 2⁽⁷⁺²) bytes before it must latch a new address. Note that the maximum number of transfers will only happen when the address's least significant bits are all 0.
 
Page Size only matters for DMA transfers; all direct access to the PI is only ever 32 bits wide.
 
==== <span style="display:none;">0x0460 00n0 - PI_BSD_DOMn_RLS ====
----
{{#invoke:Register table|head|550px|PI_BSD_DOM1_RLS <code>0x0460 0020</code><br>
PI_BSD_DOM2_RLS <code>0x0460 0030</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || colspan="2" | BSD_DOMn_RLS[1:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-2 | Undefined | Initialized to <code>0</code>
| 1-0 | PI_BSD_DOMn_RLS[7:0] | The "ReLeaSe" time is the number of FSB cycles, -1, the read or write signals must stay high before the next read or write or address cycle
}}
 
The default value for PI_BSD_DOM1_RLS is 3, meaning (3+1)·16 = 64ns, copied by IPL2 from the cartridge header.
'''TODO'''
 
= Physical Bus Pinout =
The PI Bus is a Bi-directional and MUX'edmultiplexed interface where there iswith a 16bit data path to the RomROM, 64DD, Flash Ram and SRAMcart ramRAM chips. It is used to send both the wanted address and data to and from the RCP. This is not to be confused with the serial EEPROM, CIC and RTC (real time clock) chips that go through the SI interface and PIF chip via the cartridge port as well.
{| class="wikitable"
|+
!Pin Name
!Cart pins
!Description
!Discription
|-
|AD0
|28
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[16] is latched internally in the ROM
Line 111 ⟶ 327:
|-
|AD1
|29
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[17] is latched internally in the ROM
Line 120 ⟶ 336:
|-
|AD2
|30
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[18] is latched internally in the ROM
Line 129 ⟶ 345:
|-
|AD3
|32
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[19] is latched internally in the ROM
Line 138 ⟶ 354:
|-
|AD4
|36
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[20] is latched internally in the ROM
Line 147 ⟶ 363:
|-
|AD5
|37
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[21] is latched internally in the ROM
Line 156 ⟶ 372:
|-
|AD6
|40
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[22] is latched internally in the ROM
Line 165 ⟶ 381:
|-
|AD7
|41
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[23] is latched internally in the ROM
Line 174 ⟶ 390:
|-
|AD8
|16
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[24] is latched internally in the ROM
Line 183 ⟶ 399:
|-
|AD9
|15
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[25] is latched internally in the ROM
Line 192 ⟶ 408:
|-
|AD10
|12
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[26] is latched internally in the ROM
Line 201 ⟶ 417:
|-
|AD11
|11
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[27] is latched internally in the ROM
Line 210 ⟶ 426:
|-
|AD12
|7
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[28] is latched internally in the ROM
Line 219 ⟶ 435:
|-
|AD13
|5
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[29] is latched internally in the ROM
Line 228 ⟶ 444:
|-
|AD14
|4
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[30] is latched internally in the ROM
Line 237 ⟶ 453:
|-
|AD15
|3
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[31] is latched internally in the ROM
Line 246 ⟶ 462:
|-
|/ALEH
|35
|ThisParts internallyon latchesthe PI bus are expected to latch the high address (Bits[31:16]) requested from the RCP in the rom when itthis goes from HIGH to LOW.
 
When this signal goes from LOW to HIGH it resets the internal address system so it can await for a new address request.
 
This stays HIGH when in idle and LOW when processing data. Commercial ROMs also use this as /CE, entering a low-power state while this signal is high.
 
This signal will be high for at least 7 FSB cycles, each time a new address is loaded.
|-
|/ALEL
|33
|ThisParts internallyon latchesthe PI bus are expected to latch the low address (Bits[15:0]) requested from the RCP in the rom when itthis goes from HIGH to LOW.
No action has been seen when this goes from LOW to HIGH.
 
This stays HIGH when in idle and LOW when processing data.
 
This signal will be high for at least 14 FSB cycles, each time a new address is loaded, ending 7 FSB cycles after ALEH falls.
 
|-
|/WR
|8
|This is the signal that sends a write command to the FLASH ram, SRAM or 64DD
While this signal is low, the RCP drives the PI bus with the current word of data.
When this signal goes from LOW to HIGH it the RCP will then send data (The ROM will go in to a High-z State to not affect the data bus) This will also increase the internal address counter in the FLASH/SRAM so the data is collected for the next cycle of the /WR signaling.
 
No action has been seen whenWhen this signal goes from HIGHLOW to LOW.HIGH Itexternal willparts doare the HIGHexpected to LOWrecord changethe whenvalue theat domainthat latencymoment, (PI_BSD_DOMX_RLS_REG)if counterthey hasneed it. beenThe reachedRCP and external parts are also thenexpected to increase the PI_BSD_DOMX_RLS_REGinternal address counter.(More onin thispreparation countersfor later)the next word transferred.
 
The RCP will not change this signal from HIGH to LOW until either the Latency (PI_BSD_DOMn_LAT) or Release (PI_BSD_DOMn_RLS) registers have counted the required number of FSB clocks.
This stays HIGH when in idle and LOW when processing write data.
 
This stays HIGH when idle.
|-
|/RD
|10
|This is the signal that sends a read command to the ROM, FLASH ram, SRAM or 64DD.
While this signal is low, the RCP expects that some device will drive the PI Bus.
When this signal goes from LOW to HIGH it the address selected rom/FLASH/SRAM/64DD will then send data. This will also increase the internal address counter in the ROM/FLASH/SRAM/64DD so the data is collected for the next cycle of the /RD signaling.
 
No action has been seen when this goes from HIGH to LOW. It will do the HIGH to LOW change when the domain latency (PI_BSD_DOMX_RLS_REG) counter has been reached and also then the PI_BSD_DOMX_RLS_REG counter. (More on this counters later)
 
This stays HIGH when in idle and LOW when processing Read data.
|}
 
= Parallel Interface Registers =
0x0460 0000 to 0x046F FFFF  Address range:
{| class="wikitable"
|+
!Reg Name
!Reg Address (32Bit)
!Read or Write
!Discription
|-
|PI_DRAM_ADDR_REG [23:0]
|32'h0460_0000
|R/W
|This is the starting address in RDRAM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address
|-
|PI_CART_ADDR_REG [31:0]
|32'h0460_0004
|R/W
|This is the starting address in ROM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address
|-
|PI_RD_LEN_REG [23:0]
|32'h0460_0008
|R/W
|The is the amount of bytes to be transferred from RDRAM to the ROM location (this has to be a value in a multiple of 16bits (2 Bytes)).
This number is the total amount of bytes you want to transfer - 1
|-
|PI_WR_LEN_REG [23:0]
|32'h0460_000C
|R/W
|The is the amount of bytes to be transferred from ROM to the RDRAM location (this can be byte amount but weird un-alignment issues happen. more on this later)
This number is the total amount of bytes you want to transfer - 1
|-
|PI_STATUS_REG
|32'h0460_0010
|R/W
|On Read:
Bit [0] : DMA is busy
 
Bit [1] : IO Busy
 
Bit [2] : DMA Error
 
Bit [3] : Interrupt (DMA Completed)
 
On Write:
 
Bit [0] : Reset the DMA controller and stop any transfer begin done
 
Bit [1] : Clear Interrupt
|-
|PI_BSD_DOM1_LAT_REG
 
PI_BSD_DOM2_LAT_REG [7:0]
|32'h0460_0014
 
32'h0460_0024
|R/W
|This is a 8 bit counter for the timing between sending the address to the ROM and when to read or write the block of data over the cart bus
This counter runs after the Low Address is asserted on the bus and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the bus can then start the Read or write process. Then the PI_BSD_DOMX_RLS_REG process starts for the data transfer
 
Default value set by games is (8'h40)
|-
|PI_BSD_DOM1_PWD_REG
PI_BSD_DOM2_PWD_REG
 
[7:0]
|32'h0460_0018
32'h0460_0028
|R/W
|This is a 8 bit counter for the timing on how long the Read or Write signal is to stay LOW before it can go HIGH. Once the Read signal goes high Data on the bus from the rom is read to the N64. The same is with the Write signal but the RCP outputs the data
This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to PI_BSD_DOM1_RLS_REG.
 
Default value set by games is (8'h12)
|-
|PI_BSD_DOM1_PGS_REG
PI_BSD_DOM2_PGS_REG
 
[7:0]
|32'h0460_001C
32'h0460_002C
|R/W
|This is a 4 bit counter for the timing on how many concurrent reads or writes can happen after 128 bytes of data are process and then the Cart bus has to advise to the Cart an update address.
 
Default value set by games is (4'h07)
|-
|PI_BSD_DOM1_RLS_REG
PI_BSD_DOM2_RLS_REG
 
When this signal goes from LOW to HIGH the RCP will record the value at that moment. The RCP and external parts are also expected to increase the internal address counter in preparation for the next word transferred.
[7:0]
|32'h0460_0020
32'h0460_0030
|R/W
|This is a 2 bit counter for the timing on how long the Read or Write signal is to stay HIGH before it can go LOW.
 
The /RD signal has the same timing constraints as the /WR signal above.
This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to idle or back to PI_BSD_DOMX_LAT_REG.
 
This stays HIGH when idle.
Default value set by games is (2'h3)
|}
 
Lidnariq
60

edits

Retrieved from "https://n64brew.dev/wiki/Special:MobileDiff/4615"