Peripheral Interface: Difference between revisions
Update to the phy details of the PI interface
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Mazamars312 (talk | contribs) (Update to the phy details of the PI interface) |
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=== Parallel Interface Physical bus ===
The PI Bus is a Bi-directional and MUX'ed interface where there is a 16bit data path to the Rom, 64DD, Flash Ram and SRAM ram chips is used to send both the wanted address and data to and from the RCP. This is not to be confused with the serial EEPROM, CIC and RTC (real time clock) chips that go through the SI interface and PIF chip via the cartage port as well.
{| class="wikitable"
|+
!Pin Name
!Cart pins
!Discription
|-
|AD0
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[16] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[0] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [0]
|-
|AD1
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[17] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[1] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [1]
|-
|AD2
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[18] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[2] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [2]
|-
|AD3
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[19] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[3] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [3]
|-
|AD4
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[20] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[4] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [4]
|-
|AD5
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[21] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[5] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [5]
|-
|AD6
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[22] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[6] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [6]
|-
|AD7
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[23] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[7] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [7]
|-
|AD8
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[24] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[8] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [8]
|-
|AD9
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[25] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[9] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [9]
|-
|AD10
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[26] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[10] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [10]
|-
|AD11
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[27] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[11] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [11]
|-
|AD12
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[28] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[12] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [12]
|-
|AD13
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[29] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[13] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [13]
|-
|AD14
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[30] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[14] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [14]
|-
|AD15
|
|This data bit is used with the following signals to represent the following
/ALEH - Signal changes from HIGH to LOW: Address Bit[31] is latched internally in the ROM
/ALEL - Signal changes from HIGH to LOW: Address Bit[15] is latched internally in the ROM
/WR or /RD - Signal changes from LOW to HIGH: This will read/write to that ROM location latched in the Cart. Bit [15]
|-
|/ALEH
|
|This internally latches the high address (Bits[31:16]) requested from the RCP in the rom when it goes from HIGH to LOW.
When this signal goes from LOW to HIGH it resets the internal address system so it can await for a new address request.
This stays HIGH when in idle and LOW when processing data.
|-
|/ALEL
|
|This internally latches the low address (Bits[15:0]) requested from the RCP in the rom when it goes from HIGH to LOW.
No action has been seen when this goes from LOW to HIGH.
This stays HIGH when in idle and LOW when processing data.
|-
|/WR
|
|This is the signal that sends a write command to the FLASH ram, SRAM or 64DD
When this signal goes from LOW to HIGH it the RCP will then send data (The ROM will go in to a High-z State to not affect the data bus) This will also increase the internal address counter in the FLASH/SRAM so the data is collected for the next cycle of the /WR signaling.
No action has been seen when this goes from HIGH to LOW. It will do the HIGH to LOW change when the domain latency (PI_BSD_DOMX_RLS_REG) counter has been reached and also then the PI_BSD_DOMX_RLS_REG counter.(More on this counters later)
This stays HIGH when in idle and LOW when processing write data.
|-
|/RD
|
|This is the signal that sends a read command to the ROM, FLASH ram, SRAM or 64DD.
When this signal goes from LOW to HIGH it the address selected rom/FLASH/SRAM/64DD will then send data. This will also increase the internal address counter in the ROM/FLASH/SRAM/64DD so the data is collected for the next cycle of the /RD signaling.
No action has been seen when this goes from HIGH to LOW. It will do the HIGH to LOW change when the domain latency (PI_BSD_DOMX_RLS_REG) counter has been reached and also then the PI_BSD_DOMX_RLS_REG counter. (More on this counters later)
This stays HIGH when in idle and LOW when processing Read data.
|}
=== Parallel Interface Domains ===
{| class="wikitable"
|+
!Physical Address Range
!Domain
!Common Devices
|-
|0x0500 0000 -
0x05FF FFFF
|2
|SRAM normal location (need to confirm)
|-
|0x0600 0000 -
0x07FF FFFF
|1
|64DD Boot Rom, 64DD Control Regs
|-
|0x0800 0000 -
0x0FFF FFFF
|2
|Flash Ram (need to confirm)
|-
|0x1000 0000 -
0x1FBF FFFF
|1
|Standard Game Cartage location
|-
|0x1FD0 0000 -
0x7FFF FFFF
|1
|
|}
=== Parallel Interface Registers ===
0x0460 0000 to 0x046F FFFF Address range:
Line 65 ⟶ 283:
32'h0460_0028
|R/W
|This is a 8 bit counter for the timing on how long the Read or Write signal is to stay LOW before it can go HIGH. Once the Read signal goes high Data on the bus from the rom is read to the N64. The same is with the Write signal but the RCP outputs the data
This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to PI_BSD_DOM1_RLS_REG.
Line 88 ⟶ 306:
32'h0460_0030
|R/W
|This is a 8 bit counter for the timing on how long the Read or Write signal is to stay HIGH before it can go LOW.
This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to idle or back to PI_BSD_DOMX_LAT_REG.
| |||