Peripheral Interface: Difference between revisions
Some PI data
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Mazamars312 (talk | contribs) (Some PI data) |
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!Discription
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|PI_DRAM_ADDR_REG [23:0]
|32'h0460_0000
|R/W
|This is the starting address in RDRAM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address
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|PI_CART_ADDR_REG [31:0]
|32'h0460_0004
|R/W
|This is the starting address in ROM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address
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|PI_RD_LEN_REG [23:0]
|32'h0460_0008
|R/W
|The is the amount of bytes to be transferred from RDRAM to the ROM location (this has to be a value in a multiple of 16bits (2 Bytes))
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|PI_WR_LEN_REG [23:0]
|32'h0460_000C
|R/W
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|PI_BSD_DOM1_LAT_REG
PI_BSD_DOM2_LAT_REG [7:0]
|32'h0460_0014
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|PI_BSD_DOM1_PWD_REG
PI_BSD_DOM2_PWD_REG
[7:0]
|32'h0460_0018
32'h0460_0028
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|PI_BSD_DOM1_PGS_REG
PI_BSD_DOM2_PGS_REG
[7:0]
|32'h0460_001C
32'h0460_002C
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|PI_BSD_DOM1_RLS_REG
PI_BSD_DOM2_RLS_REG
[7:0]
|32'h0460_0020
32'h0460_0030
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=== PI Interface Process ===
=== Aligned DMA Transfer ===
An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit value
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