MIPS III instructions

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The NEC VR4300 uses an instruction set that is nearly identical to that of the MIPS III Instruction Set Architecture (ISA). While the instruction set is explained in detail in the VR4300 datasheet, this article serves as a reformatted reference for those same instructions, including any quirks or additional reminders that are useful when programming something for the N64. See also MIPS Assembly.

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Instruction Notation Key

Symbol Description
base An immediate value which represents a base address
cofun Coprocessor function
r 64-bit register
rd Destination register
rs Source register
rt Temporary register
GPR General Purpose Register
GPR[r] The general purpose register 'r'
label Label name
immediate A hardcoded value via an assembler variable or literal
offset An immediate value added to base address to form a virtual address
sa Shift this number of bits left or right
sign-extended Extends the upper bits with 1's or 0's to preserve the sign and value of the number
zero-extended Extends the upper bits with 0's.


CPU Instruction Set

Every instruction has a 32-bit instruction word that the CPU uses to identify the instruction and any arguments used in it. The upper 6 bits is the instruction's opcode, however some instructions use additional constant bits to further define the operation. For example, the SPECIAL opcode is used for numerous instructions including ADD, SUB, AND, BREAK, and more.

Symbol Description
s source register number
d destination register number
t temporary register number
k literal/immediate value
b base address
f offset address
x coprocessor number


Typically an assembler will be used when programming in order to format the proper instruction word, when generating a ROM file. Most developers can safely ignore the instruction word column entirely.

However, most assemblers implement branch instructions differently! Instead of an offset value, they usually require the use of a label or absolute address.

Mnemonic Description 32-bit Instruction Word
ADD       rd, rs, rt Add rs and rt, store result in rd 0000 00ss ssst tttt dddd d000 0010 0000
ADDI      rt, rs, immediate Add sign-extended 16bit immediate and rs, store result in rt 0010 00ss ssst tttt kkkk kkkk kkkk kkkk
ADDIU     rt, rs, immediate Add sign-extended 16bit immediate and rs, store result in rt 0010 01ss ssst tttt kkkk kkkk kkkk kkkk
ADDU      rd, rs, rt Add rs and rt, store result in rd 0000 00ss ssst tttt dddd d000 0010 0001
AND       rd, rs, rt AND rs with rt, store result in rd 0000 00ss ssst tttt dddd d000 0010 0100
ANDI      rt, rs, immediate AND rs with zero-extended immediate, store result in rt 0011 00ss ssst tttt kkkk kkkk kkkk kkkk
BCzF      offset If CPz's CpCond is false, branch to address (delay slot + offset) 0100 xx01 0000 0000 ffff ffff ffff ffff
BCzFL     offset If CPz's CpCond is false, branch to address (delay slot + offset), otherwise discard delay slot instruction 0100 xx01 0000 0010 ffff ffff ffff ffff
BCzT      offset If CPz's CpCond is true, branch to address (delay slot + offset) 0100 xx01 0000 0001 ffff ffff ffff ffff
BCzTL     offset If CPz's CpCond is true, branch to address (delay slot + offset), otherwise discard delay slot instruction 0100 xx01 0000 0011 ffff ffff ffff ffff
BEQ       rs, rt, offset If rs equals rt, branch to address (delay slot + offset) 0001 00ss ssst tttt ffff ffff ffff ffff
BEQL      rs, rt, offset If rs equals rt, branch to address (delay slot + offset), otherwise discard delay slot instruction 0101 00ss ssst tttt ffff ffff ffff ffff
BGEZ      rs, offset If rs is greater than or equal to zero, branch to address (delay slot + offset) 0000 01ss sss0 0001 ffff ffff ffff ffff
BGEZAL    rs, offset If rs is greater than or equal to zero, branch to address (delay slot + offset) and store next address to r31 0000 01ss sss1 0001 ffff ffff ffff ffff
BGEZALL   rs, offset If rs is greater than or equal to zero, branch to address (delay slot + offset) and store next address to r31, otherwise discard delay slot instruction 0000 01ss sss1 0011 ffff ffff ffff ffff
BGEZL     rs, offset If rs is greater than or equal to zero, branch to address (delay slot + offset), otherwise discard delay slot instruction 0000 01ss sss0 0011 ffff ffff ffff ffff
BGTZ      rs, offset If rs is greater than zero, branch to address (delay slot + offset) 0001 11ss sss0 0000 ffff ffff ffff ffff
BGTZL     rs, offset If rs is greater than zero, branch to address (delay slot + offset), otherwise discard delay slot instruction 0101 11ss sss0 0000 ffff ffff ffff ffff
BLEZ      rs, offset If rs is less than or equal to zero, branch to address (delay slot + offset) 0001 10ss sss0 0000 ffff ffff ffff ffff
BLEZL     rs, offset If rs is less than or equal to zero, branch to address (delay slot + offset), otherwise discard delay slot instruction 0101 10ss sss0 0000 ffff ffff ffff ffff
BLTZ      rs, offset If rs is less than zero, branch to address (delay slot + offset) 0000 01ss sss0 0000 ffff ffff ffff ffff
BLTZAL    rs, offset If rs is less than zero, branch to address (delay slot + offset) and store next address to r31 0000 01ss sss1 0000 ffff ffff ffff ffff
BLTZALL   rs, offset If rs is less than zero, branch to address (delay slot + offset) and store next address to r31, otherwise discard delay slot instruction 0000 01ss sss1 0010 ffff ffff ffff ffff
BLTZL     rs, offset If rs is less than zero, branch to address (delay slot + offset), otherwise discard delay slot instruction 0000 01ss sss0 0010 ffff ffff ffff ffff
BNE       rs, rt, offset If rs is not equal to rt, branch to address (delay slot + offset) 0001 01ss ssst tttt ffff ffff ffff ffff
BNEL      rs, rt, offset If rs is not equal to rt, branch to address (delay slot + offset), otherwise discard delay slot instruction 0101 01ss ssst tttt ffff ffff ffff ffff
BREAK       Causes breakpoint exception 0000 00kk kkkk kkkk kkkk kkkk kk00 1101
CACHE     op, offset(base) Flush instruction or data cache at address (base + offset) to RAM 1011 11bb bbbk kkkk ffff ffff ffff ffff
CFCz      rt, rd Copy contents of CPz control register rd, to GPR rt 0100 xx00 010t tttt dddd d000 0000 0000
COPz      cofun Perform coprocessor operation 0100 xx1k kkkk kkkk kkkk kkkk kkkk kkkk
CTCz      rt, rd Copy contents of GPR rt, to CPz control register rd 0100 xx00 110t tttt dddd d000 0000 0000
DADD      rd, rs, rt Add rs and rt, store result in rd (mode restrictions) 0000 00ss ssst tttt dddd d000 0010 1100
DADDI     rt, rs, immediate Add sign-extended 16bit immediate and rs, store result in rt (mode restrictions) 0110 00ss ssst tttt kkkk kkkk kkkk kkkk
DADDIU    rt, rs, immediate Add sign-extended 16bit immediate and rs, store result in rt (mode restrictions) 0110 01ss ssst tttt kkkk kkkk kkkk kkkk
DADDU     rd, rs, rt Add rs and rt, store result in rd (mode restrictions) 0000 00ss ssst tttt dddd d000 0010 1101
DDIV      rs, rt Divide signed rs by signed rt, store quotient in register LO and remainder in HI (mode restrictions) 0000 00ss ssst tttt 0000 0000 0001 1110
DDIVU     rs, rt Divide unsigned rs by unsigned rt, store quotient in register LO and remainder in HI (mode restrictions) 0000 00ss ssst tttt 0000 0000 0001 1111
DIV       rs, rt Divide signed rs by signed rt, store quotient in register LO and remainder in HI 0000 00ss ssst tttt 0000 0000 0001 1010
DIVU      rs, rt Divide unsigned rs by unsigned rt, store quotient in register LO and remainder in HI 0000 00ss ssst tttt 0000 0000 0001 1011
DMFC0     rt, rd Copy doubleword contents of CPz coprocessor register rd, to GPR rt 0100 0000 001t tttt dddd d000 0000 0000
DMTC0     rt, rd Copy doubleword contents of GPR rt, to CPz coprocessor register rd 0100 0000 101t tttt dddd d000 0000 0000
DMULT     rs, rt Multiply signed rs with signed rt, store low-order doubleword in LO, and high-order doubleword to HI (mode restrictions) 0000 00ss ssst tttt 0000 0000 0001 1100
DMULTU    rs, rt Multiply unsigned rs with unsigned rt, store low-order doubleword in LO, and high-order doubleword to HI (mode restrictions) 0000 00ss ssst tttt 0000 0000 0001 1101
DSLL      rd, rt, sa Shift rt left by sa bits, store result in rd (mode restrictions) 0000 0000 000t tttt dddd dkkk kk11 1000
DSLLV     rd, rt, rs Shift rt left by rs (limited to 63), store result in rd (mode restrictions) 0000 00ss ssst tttt dddd d000 0001 0100
DSLL32    rd, rt, rs Shift rt left by (32 + sa) bits, store result in rd (mode restrictions) 0000 0000 000t tttt dddd dkkk kk11 1100
DSRA      rd, rt, sa Shift rt right by sa bits, store sign-extended result in rd (mode restrictions) 0000 0000 000t tttt dddd dkkk kk11 1011
DSRAV     rd, rt, rs Shift rt right by rs (limited to 63), store sign-extended result in rd (mode restrictions) 0000 00ss ssst tttt dddd d000 0001 0111
DSRA32    rd, rt, sa Shift rt right by (32 + sa) bits, store sign-extended result in rd (mode restrictions) 0000 0000 000t tttt dddd dkkk kk11 1111
DSRL      rd, rt, sa Shift rt right by sa bits, store zero-extended result in rd (mode restrictions) 0000 0000 000t tttt dddd dkkk kk11 1010
DSRLV     rd, rt, rs Shift rt right by rs (limited to 63), store zero-extended result in rd (mode restrictions) 0000 00ss ssst tttt dddd d000 0001 0110
DSRL32    rd, rt, sa Shift rt right by (32 + sa) bits, store zero-extended result in rd (mode restrictions) 0000 0000 000t tttt dddd dkkk kk11 1110
DSUB      rd, rs, rt Subtract rt from rs, store result in rd 0000 00ss ssst tttt dddd d000 0010 1110
DSUBU     rd, rs, rt Subtract rt from rs, store result in rd 0000 00ss ssst tttt dddd d000 0010 1111
ERET        Return from interrupt, exception, or error exception 0100 0010 0000 0000 0000 0000 0001 1000
J         target Jump to target address 0000 10kk kkkk kkkk kkkk kkkk kkkk kkkk
JAL       target Jump to target address, stores return address in r31 0000 11kk kkkk kkkk kkkk kkkk kkkk kkkk
JALR      rd, rs Jump to address stored in rs, stores return address in rd 0000 00ss sss0 0000 dddd d000 0000 1001
JALR      rs Jump to address stored in rs, stores return address in r31 0000 00ss sss0 0000 1111 1000 0000 1001
JR        rs Jump to address stored in rs 0000 00ss sss0 0000 0000 0000 0000 1000
LB        rt, offset(base) Loads byte stored at memory address (base + offset), stores sign-extended byte in rt 1000 00bb bbbt tttt ffff ffff ffff ffff
LBU       rt, offset(base) Loads byte stored at memory address (base + offset), stores zero-extended byte in rt 1001 00bb bbbt tttt ffff ffff ffff ffff
LD        rt, offset(base) Loads doubleword stored at memory address (base + offset), stores doubleword in rt 1101 11bb bbbt tttt ffff ffff ffff ffff
LDCz      rt, offset(base) Copies doubleword stored at memory address (base + offset), to CPz 1101 xxbb bbbt tttt ffff ffff ffff ffff
LDL       rt, offset(base) Loads a portion of a doubleword beginning at memory address (base + offset), stores 1-8 bytes in high-order portion of rt 0110 10bb bbbt tttt ffff ffff ffff ffff
LDR       rt, offset(base) Loads a portion of a doubleword beginning at memory address (base + offset), stores 1-8 bytes in low-order portion of rt 0110 11bb bbbt tttt ffff ffff ffff ffff
LH        rt, offset(base) Loads halfword stored at memory address (base + offset), stores sign-extended halfword in rt 1000 01bb bbbt tttt ffff ffff ffff ffff
LHU       rt, offset(base) Loads halfword stored at memory address (base + offset), stores zero-extended halfword in rt 1001 01bb bbbt tttt ffff ffff ffff ffff
LL        rt, offset(base) Load Linked (Refer to section below) 1100 00bb bbbt tttt ffff ffff ffff ffff
LLD       rt, offset(base) Load Linked Doubleword (Refer to section below) 1101 00bb bbbt tttt ffff ffff ffff ffff
LUI       rt, immediate 16-bit immediate is shifted left 16 bits using trailing zeros, result placed in rt 0011 1100 000t tttt kkkk kkkk kkkk kkkk
LW        rt, offset(base) Loads word stored at memory address (base + offset), stores sign-extended word in rt 1000 11bb bbbt tttt ffff ffff ffff ffff
LWCz      rt, offset(base) Copies word stored at memory address (base + offset), to CPz 1100 xxbb bbbt tttt ffff ffff ffff ffff
LWL       rt, offset(base) Loads a portion of a word beginning at memory address (base + offset), stores 1-4 bytes in high-order portion of rt 1000 10bb bbbt tttt ffff ffff ffff ffff
LWR       rt, offset(base) Loads a portion of a word beginning at memory address (base + offset), stores 1-4 bytes in low-order portion of rt 1001 10bb bbbt tttt ffff ffff ffff ffff
LWU       rt, offset(base) Loads word stored at memory address (base + offset), stores zero-extended word in rt 1001 11bb bbbt tttt ffff ffff ffff ffff
MFC0      rt, rd Copy contents of CP0's coprocessor register rd, to GPR rt 0100 0000 000t tttt dddd d000 0000 0000
MFCz      rt, rd Copy contents of CPz's coprocessor register rd, to GPR rt 0100 xx00 000t tttt dddd d000 0000 0000
MFHI      rd Copy contents of register HI to rd (warning: hazard) 0000 0000 0000 0000 dddd d000 0001 0000
MFLO      rd Copy contents of register LO to rd (warning: hazard) 0000 0000 0000 0000 dddd d000 0001 0010
MTC0      rt, rd Copy contents of GPR rt, to CP0's coprocessor register rd 0100 0000 100t tttt dddd d000 0000 0000
MTCz      rd, rd Copy contents of GPR rt, to CPz's coprocessor register rd 0100 xx00 100t tttt dddd d000 0000 0000
MTHI      rs Copy contents of rs to register HI 0000 00ss sss0 0000 0000 0000 0001 0001
MTLO      rs Copy contents of rs to register LO 0000 00ss sss0 0000 0000 0000 0001 0011
MULT      rs, rt Multiply signed rs by signed rt, store low-order word of result in register LO and high-order word in HI 0000 00ss ssst tttt 0000 0000 0001 1000
MULTU     rs, rt Multiply unsigned rs by unsigned rt, store low-order word of result in register LO and high-order word in HI 0000 00ss ssst tttt 0000 0000 0001 1001
NOR       rd, rs, rt NOR rs and rt, store result in rd 0000 00ss ssst tttt dddd d000 0010 0111
OR        rd, rs, rt OR rs and rt, store result in rd 0000 00ss ssst tttt dddd d000 0010 0101
ORI       rt, rs, immediate OR rs and zero-extended immediate, store result in rt 0011 01ss ssst tttt kkkk kkkk kkkk kkkk
SB        rt, offset(base) Stores least-significant byte from rt, to memory address (base + offset) 1010 00bb bbbt tttt ffff ffff ffff ffff
SC        rt, offset(base) If LL bit is set, stores contents of rt, to memory address (base + offset) 1110 00bb bbbt tttt ffff ffff ffff ffff
SCD       rt, offset(base) If LLD bit is set, stores contents of rt, to memory address (base + offset) (mode restrictions) 1111 00bb bbbt tttt ffff ffff ffff ffff
SD        rt, offset(base) Stores doubleword from rt, to memory address (base + offset) 1111 11bb bbbt tttt ffff ffff ffff ffff
SDCz      rt, offset(base) Copies doubleword from CPz, to memory address (base + offset) 1111 xxbb bbbt tttt ffff ffff ffff ffff
SDL       rt, offset(base) Loads a portion of rt, stores 1-8 bytes in high-order portion of memory address (base + offset) 1011 00bb bbbt tttt ffff ffff ffff ffff
SDR       rt, offset(base) Loads a portion of rt, stores 1-8 bytes in low-order portion of memory address (base + offset) 1011 01bb bbbt tttt ffff ffff ffff ffff
SH        rt, offset(base) Stores halfword from rt, to memory address (base + offset) 1010 01bb bbbt tttt ffff ffff ffff ffff
SLL       rd, rt, sa Shift rt left by sa bits, store result in rd 0000 0000 000t tttt dddd dkkk kk00 0000
SLLV      rd, rt, rs Shift rt left by rs (limited to 31), store result in rd 0000 00ss ssst tttt dddd d000 0000 0100
SLT       rd, rs, rt If signed rs is less than signed rt, store one in rd, otherwise store zero 0000 00ss ssst tttt dddd d000 0010 1010
SLTI      rt, rs, immediate If signed rs is less than sign-extended immediate, store one in rd, otherwise store zero 0010 10ss ssst tttt kkkk kkkk kkkk kkkk
SLTIU     rt, rs, immediate If unsigned rs is less than sign-extended immediate, store one in rt, otherwise store zero 0010 11ss ssst tttt kkkk kkkk kkkk kkkk
SLTU      rd, rs, rt If unsigned rs is less than unsigned rt, store one in rd, otherwise store zero 0000 00ss ssst tttt dddd d000 0010 1011
SRA       rd, rt, sa Shift rt right by sa bits, store sign-extended result in rd 0000 0000 000t tttt dddd dkkk kk00 0011
SRAV      rd, rt, rs Shift rt right by rs (limited to 31), store sign-extended result in rd 0000 00ss ssst tttt dddd d000 0000 0111
SRL       rd, rt, sa Shift rt right by sa bits, store zero-extended result in rd 0000 0000 000t tttt dddd dkkk kk00 0010
SRLV      rd, rt, rs Shift rt right by rs (limited to 31), store zero-extended result in rd 0000 00ss ssst tttt dddd d000 0000 0110
SUB       rd, rs, rt Subtract rt from rs, store result in rd 0000 00ss ssst tttt dddd d000 0010 0010
SUBU      rd, rs, rt Subtract rt from rs, store result in rd 0000 00ss ssst tttt dddd d000 0010 0011
SW        rt, offset(base) Stores word from rt, to memory address (base + offset) 1010 11bb bbbt tttt ffff ffff ffff ffff
SWCz      rt, offset(base) Copies word from CPz, to memory address (base + offset) 1110 xxbb bbbt tttt ffff ffff ffff ffff
SWL       rt, offset(base) Loads a portion of rt, stores 1-4 bytes in high-order portion of memory address (base + offset) 1010 10bb bbbt tttt ffff ffff ffff ffff
SWR       rt, offset(base) Loads a portion of rt, stores 1-4 bytes in low-order portion of memory address (base + offset) 1011 10bb bbbt tttt ffff ffff ffff ffff
SYNC        Executed as NOP on the VR4300 0000 0000 0000 0000 0000 0000 0000 1111
SYSCALL     Causes system call exception 0000 00kk kkkk kkkk kkkk kkkk kk00 1100
TEQ       rs, rt If rs equals rt, cause a trap exception 0000 00ss ssst tttt kkkk kkkk kk11 0100
TEQI      rs, immediate If rs equals sign-extended immediate, cause a trap exception 0000 01ss sss0 1100 kkkk kkkk kkkk kkkk
TGE       rs, rt If signed rs is greater than or equal to signed rt, cause a trap exception 0000 00ss ssst tttt kkkk kkkk kk11 0000
TGEI      rs, immediate If signed rs is greater than or equal to sign-extended immediate, cause a trap exception 0000 01ss sss0 1000 kkkk kkkk kkkk kkkk
TGEIU     rs, immediate If unsigned rs is greater than or equal to sign-extended immediate, cause a trap exception 0000 01ss sss0 1001 kkkk kkkk kkkk kkkk
TGEU      rs, rt If unsigned rs is greater than or equals to unsigned rt, cause a trap exception 0000 00ss ssst tttt kkkk kkkk kk11 0001
TLBP        Searches for a TLB entry that matches the EntryHi register 0100 0010 0000 0000 0000 0000 0000 1000
TLBR        Loads EntryHi and EntryLo registers with the TLB entry pointed at by the Index register 0100 0010 0000 0000 0000 0000 0000 0001
TLBWI       Stores the contents of EntryHi and EntryLo registers into the TLB entry pointed at by the Index register 0100 0010 0000 0000 0000 0000 0000 0010
TLBWR       Stores the contents of EntryHi and EntryLo registers into the TLB entry pointed at by the Random register 0100 0010 0000 0000 0000 0000 0000 0110
TLT       rs, rt If signed rs is less than signed rt, cause a trap exception 0000 00ss ssst tttt kkkk kkkk kk11 0010
TLTI      rs, immediate If signed rs is less than sign-extended immediate, cause a trap exception 0000 01ss sss0 1010 kkkk kkkk kkkk kkkk
TLTIU     rs, immediate If unsigned rs is less than sign-extended immediate, cause a trap exception 0000 01ss sss0 1011 kkkk kkkk kkkk kkkk
TLTU      rs, rt If unsigned rs is less than unsigned rt, cause a trap exception 0000 00ss ssst tttt kkkk kkkk kk11 0011
TNE       rs, rt If rs does not equal rt, cause a trap exception 0000 00ss ssst tttt kkkk kkkk kk11 0110
TNEI      rs, immediate If rs does not equal sign-extended immediate, cause a trap exception 0000 01ss sss0 1110 kkkk kkkk kkkk kkkk
XOR       rd, rs, rt XOR rs with rt, store result in rd 0000 00ss ssst tttt dddd d000 0010 0110
XORI      rt, rs, immediate XOR rs with zero-extended immediate, store result in rd 0011 10ss ssst tttt kkkk kkkk kkkk kkkk


Hazards

The mfhi and mflo instructions will produce incorrect results if any of the two following instructions modify the HI and LO registers, respectively. Note that by default, assemblers other than Bass will prevent this by reordering instructions or inserting nop. If you are using .set noreorder or Bass, you must ensure this yourself.

ADD

Format: ADD rd, rs, rt

Description:
The contents of general purpose register rs and the contents of general purpose register rt are added to store the result in general purpose register rd. In 64-bit mode, the operands must be sign-extended, 32-bit values. An integer overflow exception occurs if the carries out of bits 30 and 31 differ (2’s complement overflow). The contents of destination register rd is not modified when an integer overflow exception occurs.
Operation:
32: GPR[rd] ← GPR[rs] + GPR[rt]

64: temp ← GPR[rs] + GPR[rt]
    GPR[rd] ← (temp31)32 || temp31...0
Exceptions:
Integer overflow exception

ADDI

Format: ADDI rt, rs, immediate

Description:
The 16-bit immediate is sign-extended and added to the contents of general purpose register rs to store the result in general purpose register rt. In 64-bit mode, the operand must be sign-extended, 32-bit values. An integer overflow exception occurs if carries out of bits 30 and 31 differ (2’s complement overflow). The contents of destination register rt is not modified when an integer overflow exception occurs.
Operation:
32: GPR[rt] ← GPR[rs] + (immediate15)16 || immediate15...0

64: temp ← GPR[rt] ← GPR[rs] + (immediate15)48 || immediate15...0
    GPR[rd] ← (temp31)32 || temp31...0
Exceptions:
Integer overflow exception

FPU Instruction Set

The floating point unit (FPU) is contained within the VR3400 microprocessor and handles floating point operations. The FPU uses a different set of registers for its operations (f0 - f31). While these registers are separate from general purpose registers, they function the same way.

Symbol Description
fd Destination register
fs Source register
ft Temporary register
fmt Operand format
FPR Floating-point Register

Many FPU instructions require an operand format fmt. This format dictates the size of the operators and whether they are floating-point or fixed-point, as noted in this table:

Symbol Description
S 32 bits, floating-point
D 64 bits, floating-point
W 32 bits, fixed-point
L 64 bits, fixed-point

Some instructions will also require a conditional cond. This determines what kind of comparison is performed.

Symbol Description
- table incomplete
F T
UN OR
EQ NEQ
UEQ OGL
OLT UGE
ULT OGE
OLE UGT
ULE OGT
SF ST
NGLE GLE
SEQ SNE
NGL GL
LT NLT
NGE GE
LE NLE
NGT GT

Instruction Word Key

Symbol Description
s source register number
d destination register number
t temporary register number
k literal/immediate value
b base address
f offset address
x coprocessor number
a fmt - operand format
c cond - conditional
Mnemonic Description 32-bit Instruction Word
ABS.fmt   fd, fs Absolute value of fs, store result in fd 0100 01aa aaa0 0000 ssss sddd dd00 0101
ADD.fmt   fd, fs Add fs and ft, store result in fd 0100 01aa aaat tttt ssss sddd dd00 0000
C.cond.fmtfs, ft Compares fs and ft using cond 0100 01aa aaat tttt ssss s000 0011 cccc
BC1F      offset   0100 0101 0000 0000 ffff ffff ffff ffff
BC1FL     offset   0100 0101 0000 0010 ffff ffff ffff ffff
BC1T      offset   0100 0101 0000 0001 ffff ffff ffff ffff
BC1TL     offset   0100 0101 0000 0011 ffff ffff ffff ffff


Pseudo-Instructions

Many assemblers, regardless of architecture, will add additional instructions to assist developers. This table shows the instructions added by the bass assembler, which is commonly used to develop N64 ROMs.