Video Interface

Introduction

The Video Interface Registers provide a lot of flexibility, the exact same chips and registers are used to support NTSC, PAL and M-PAL. Below each register will be explained using sample data to clarify how it should be used. All registers are 32-bits in length and should always be written a full word (32-bits) at a time.

Video DAC

The Video DAC has a 7 bit multiplexed data bus that is used to generate the video signal from the RCP. This allows the N64 to output a 21 bit color output even thou internally it can do 24 bits. Why this lower bit was not used is not explained in any documentation found at this moment.

Video DAC Bus and waveform. Image from: http://members.optusnet.com.au/eviltim/n64rgb/n64rgb.html

The Video DAC clock runs at 4 times the speed of the internal pixel clock so the multiplexing can happen on the VI bus. This 4 clock process outputs the RGB colors and the VSync, Hsync, Clamp and Csync and is reset using a dsync reset signal. This is driven by a pixel clock provided by the MX8330 (IC U7)

	Cycle 1	Cycle 2	Cycle 3	Cycle 4
D0	Red 0	Green 0	Blue 0	!Csync
D1	Red 1	Green 1	Blue 1	!Hsync
D2	Red 2	Green 2	Blue 2	!Clamp
D3	Red 3	Green 3	Blue 3	!Vsync
D4	Red 4	Green 4	Blue 4	NA
D5	Red 5	Green 5	Blue 5	NA
D6	Red 6	Green 6	Blue 6	NA
DSYNC	HIGH	HIGH	HIGH	Low

There are 3 different pixel clocks that are used in the N64 for the 3 TV standards:

• 

  Mx8330 video clock maths and fselect

TV Signal Type	Pixel Clock	MX8330 Input clock	MX8330 FSEL input	Clock Maths using datasheet
NTSC	48.62Mhz	14.3Mhz	HIGH	((14.3 * 4 )* 17) / 5
PAL	48.72Mhz	17.4Mhz	LOW	((17.4 * 4 )* 14) / 5
MPAL	To be advised	To be advised	To be advised

Video Standards

The video standards send more than just pixel data both on each line and with additional lines at the top and bottom of a frame.

Hardware

Most of the Video Interface is implemented inside the RCP (Reality CoProcessor), although there is a Video DAC (Digital Analog Converter) on the mainboard, and another encoder IC (ENC-NUS) which which appears to manage some of the signal differences between Composite and S-Video Output.

Base Address - 0x0440'0000

N64 Addressing can be complicated, so to keep it simple use the following conventions:

• Use 0xA in the leading zero position (0xA440'0000) to write directly to the memory location.

When using the VI Interface this should be all you need. For other Interfaces there are some situations that it should be accessed with a different technique, so they will be covered in more depth where it's relevant.

0x0440 0000 - VI_CTRL

---

VI_CTRL 0x0440 0000
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
	—	—	—	—	—	—	—	—
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	RW-0
	—	—	—	—	—	—	—	DITHER_FILTER_ENABLE
15:8	RW-0	RW-0	RW-0	RW-0	RW-0	U-0	RW-0	RW-0
	PIXEL_ADVANCE<3:0>				KILL_WE	—	AA_MODE<1:0>
7:0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	TEST_MODE	SERRATE	VBUS_CLOCK_ENABLE	DIVOT_ENABLE	GAMMA_ENABLE	GAMMA_DITHER_ENABLE	TYPE<1:0>

bit 31-17	Unimplemented: Read as 0
bit 16	DITHER_FILTER_ENABLE: Dither Enable bit 1 = Dither filter is enabled (normally used for 16-bit color) 0 = Dither filter is disabled (normally used for 32-bit color)     Using the filter disables the dithering effects. It's generally assumed that if enabled, dithering would occur in the RDP instead.
bit 15-12	PIXEL_ADVANCE<3:0>: Use 0b0011 for most effective behavior
bit 11	KILL_WE: Diagnostics only
bit 10	Unimplemented: Read as 0
bit 9-8	AA_MODE<1:0>: Anti-Alias Mode 11 = AA and resampling disabled, replicate pixels without interpolation 10 = AA disabled, resampling enabled, and operate as if everything is covered 01 = AA enabled, resampling enabled, and only fetches extra lines as needed 00 = AA enabled, resampling enabled, and will always fetch extra lines
bit 7	TEST_MODE: Diagnostics only
bit 6	SERRATE: Normally enabled if interlacing, otherwise disabled 1 = Enabled 0 = Disabled
bit 5	VBUS_CLOCK_ENABLE: Vbus Clock Enable 1 = Vbus clock enabled 0 = Vbus clock disabled     Warning: Always leave disabled! Setting this bit enables a second driver, which when enabled will output on the same pin as another driver, possibly causing physical console damage.
bit 4	DIVOT_ENABLE: Fixes minor artifacts left over from anti-aliasing (more details below) 1 = Enabled (usually used if AA is enabled) 0 = Disabled
bit 3	GAMMA_ENABLE: Fixes non-linear gamma in TV screens (more details below) 1 = Enabled 0 = Disabled
bit 2	GAMMA_DITHER_ENABLE: Adds randomized noise to the video output, in the least significant bits to remove mach banding artifacts 1 = Enabled (usually set unless banding artifacts are desired for extra effect) 0 = Disabled
bit 1-0	TYPE<1:0>: Video pixel size, also known as color bit depth 11 = 8/8/8/8 (32 bit color) 10 = 5/5/5/3 (16 bit color, technically 18 bits wide) 01 = reserved 00 = blank (no data and no sync, TV screens will either show static or nothing)

---

0x0440 0004 - VI_DRAM_ADDR_REG - R/(W default)

This is the address of the FrameBuffer that should be sent to the TV, it's nice that the buffer doesn't have to be copied and can be sent directly to the TV. If you are using double or triple buffered screens this is the value that you will be changing to display the next screen.

0x0440 0008 - VI_H_WIDTH_REG - R/(W default)

This is the width in pixels of the framebuffer if you draw to the framebuffer based on a different width than what is given here the image will drift with each line to the left or right. The common values are 320 and 640, the maximum value is 640. The minimum value depends on the TV set, 160 would probably be a safe minimum but no guarantee. The same value would also be used on drawing commands for clipping or scissors. This can also be used with High Res interlacing modes to change the odd and even lines of the framebuffer to be drawn to screen by doubling the width of this value and changing the VI_DRAM_ADDR_REG to the odd or even field being displayed.

0x0440 000C - VI_V_INTR_REG - R/(W default)

This is the Vertical Interrupt configuration register, when the VI is sending lines to the TV when it reaches this line it will trigger a VI Interrupt. The line number entered here is usually the last one that has pixel data. This is the ideal time to swap the frame buffer, because you want to do this while the non-pixel data is being sent.

0x0440 0010 - VI_V_CURRENT_LINE_REG - RO (Read Only/Writes ignored)

This is the line that the VI is currently sending to the TV.

If interrupts are used, writing to this reg will reset the interrupt line in the RCP for the the next frame (this mostly affects the address 32x04300008 and bit 3 for the VI interrupt)

0x0440 0014 - VI_BURST

---

VI_BURST 0x0440 0014
31:24	U-0	U-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	—	—	BURST_START<9:4>
23:16	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	BURST_START<3:0>				VSYNC_WIDTH<3:0>
15:8	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	BURST_WIDTH<7:0>
7:0	RW-1	RW-1	RW-0	RW-1	RW-0	RW-0	RW-0	RW-1
	HSYNC_WIDTH<7:0>

bit 31-30	Unimplemented: Read as 0
bit 29-20	BURST_START<9:0>: Start of color burst in pixels from hsync
bit 19-16	VSYNC_WIDTH<3:0>: Vertical sync width in half lines
bit 15-8	BURST_WIDTH<7:0>: Color burst width in pixels
bit 7-0	HSYNC_WIDTH<7:0>: Horizontal sync width in pixels Default value of 0xD1

Examples:

NTSC @ any resolution is 0x03E52239

• horizontal sync width in pixels: 57 (decimal)
• color burst width in pixels: 34 (decimal)
• vertical sync width in half lines: 5 (decimal)
• start of color burst in pixels from h-sync: 62 (decimal)

PAL @ any resolution is 0x0404233A

• horizontal sync width in pixels: 58 (decimal)
• color burst width in pixels: 35 (decimal)
• vertical sync width in half lines: 4 (decimal)
• start of color burst in pixels from h-sync: 64 (decimal)

---

0x0440 0018 - VI_V_SYNC_REG - R/(W default)

Always set to the Appropriate value for the Standard being used

This is the total number of lines both visible and non-visible that must be sent to the TV (based on the the standard for NTSC/PAL)

NTSC: 0x20D = 525

PAL: 0x271 = 625

0x0440 001C - VI_H_SYNC_REG

Always set to the Appropriate value for the Standard being used

• [11:0] total duration of a line in 1/4 pixel units
• [20:16] a 5-bit leap pattern used for PAL only (h_sync_period)

NTSC: 1/4 pixel width = 0xC15 = 3093

PAL: 0x00150c69 = 10101 0000 1100'0110'1001

• 1/4 pixel width = 3177
• pattern = 10101 = 21

0x0440 0020 - VI_H_SYNC_LEAP_REG

Always set to the Appropriate value for the Standard being used

• [11:0] identical to h_sync_period
• [27:16] identical to h_sync_period

NTSC: 0x0c150c15

• h_sync_period: 0x0c15 = 3093
• h_sync_period: 0x0c15 = 3093

PAL: 0x0c6f0c6e

• h_sync_period: 0x0c6e = 3182
• h_sync_period: 0x0c6f = 3183

0x0440 0024 - VI_H_START_REG

• [9:0] end of active video in screen pixels - This advised the VI core where the Start of the image is in terms of the video signal on the horizontal plane - this uses the pixel clock / 4 to align the signal to the screen
• [25:16] start of active video in screen pixels - This advised the VI core where the Start of the image is in terms of the video signal on the horizontal plane - this uses the pixel clock / 4 to align the signal to the screen

NTSC: 0x006c02ec = 0000'00 00'0110'1100 0000'00 10'1110'1100

• end of visible pixels on a line: 748 pixels
• start of visible pixels on a line: 108 pixels

PAL: 0x00800300 = 0000'00 00'1000'0000 0000'00 11'0000'0000

• end of visible pixels on a line: 768 pixels
• start of visible pixels on a line: 128 pixels

0x0440 0028 - VI_V_START_REG

• [9:0] end of active video in screen half-lines - This advised the VI core where the end of the image is in terms of the video signal on the Vertiall plane - this uses the pixel clock / 4 to align the signal to the screen
• [25:16] start of active video in screen half-lines - This advised the VI core where the start of the image is in terms of the video signal on the Vertiall plane - this uses the pixel clock / 4 to align the signal to the screen

NTSC: 0x002501ff = 0000'00 00'0010'0101 0000'00 01'1111'1111

• end of active video in screen half-lines: 511
• start of active video in screen half-lines 37

PAL: 0x005f0239 = 0000'00 00'0101'1111 0000'00 10'0011'1001

• end of active video in screen half-lines: 569
• start of active video in screen half-lines 95

0x0440 002C - VI_V_BURST_REG

Always set to the Appropriate value for the Standard being used

• [9:0] end of color burst enable in half-lines
• [25:16] start of color burst enable in half-lines

NTSC: 0x000e0204 = 0000'00 00'0000'1110 0000'00 10'0000'0100

• end of color burst enable in half-lines: 516
• start of color burst enable in half-lines: 14

PAL: 0x0009026b = 0000'00 00'0000'1001 000000 10'0110'1011

• end of color burst enable in half-lines: 619
• start of color burst enable in half-lines: 9

0x0440 0030 - VI_X_SCALE_REG

• [11:0] 1/horizontal scale up factor (2.10 format)
• [27:16] horizontal subpixel offset (2.10 format)

NTSC: 0x00000334

• 1/horizontal scale up factor (2.10 format)
• horizontal subpixel offset (2.10 format)

PAL: 0x0000019A

• 1/horizontal scale up factor (2.10 format)
• horizontal subpixel offset (2.10 format)

0x0440 0034 - VI_Y_SCALE_REG

• [11:0] 1/vertical scale up factor (2.10 format)
• [27:16] vertical subpixel offset (2.10 format)

NTSC: 0x00000400 = 0100'0000'0000

• 1/vertical scale up factor: 1.0
• vertical subpixel offset: 0.0

PAL: 0x02000800 = 0000 0010'0000'0000 0000 1000'0000'0000

• 1/vertical scale up factor: 1000'0000'0000 = 2.0
• vertical subpixel offset: 0010'0000'0000 = 0.5

How to use this information

Interlace Mode

The NTSC (and PAL) standard support interlace mode which is commonly associated with high resolution, but it can be used for more than that.

• High Resolution Mode
• Improve the visible detail of the image
• 60 frames per second in low resolution

High Resolution Mode

High resolution mode supports up to 480 lines (NTSC) while low resolution is 240 lines (NTSC). The Image doesn't magically grow or shrink because first the even lines are drawn on the screen, then it goes back to the top and draws the odd lines. If your game only draws the even lines then on a larger display you may have the image scanlines with smaller black lines visible between them.

In order to implement this feature it requires the VI_V_START_REG to be modified on every VI Interrupt, so that it outputs even lines then odd lines as needed.

NTSC Alternates between: 0x002301fd and 0x002501ff

PAL Alternates between: 0x005f0239 and 0x005d0237

Once this is explained I believe it will be fixed soon, so this is explained as an example of what the difference can be. The libdragon homebrew library doesn't actually support High Resolution Mode, because it doesn't implement this register value change. To be fair this is very easy to overlook, it works fine in every emulator and would at least look OK on a console. The difference is that emulators present the framebuffer memory as a single block of data. While the VI Interface and Video DAC see the 1 framebuffer as even lines top to bottom, then odd lines top to bottom.

Learnt from Factor 5 games(Mazamars312):

The VI_DRAM_ADDR_REG address is set to the odd or even line of the framebuffer and the VI_H_WIDTH_REG value is doubled to help skip to the next Odd or Even field line for the VI core to process.

Once the odd or even field has been displayed the VI_DRAM_ADDR_REG is updated to the other field's address. Also the VI_Y_SCALE_REG.Subpixel is changed between fields with the values 12'h0100 and 12'h0200 to help the scaling and AA calculations (Need to find out which one is Odd and Even based as this could be game based)

The real width and height values are calculated by the following calculations

Width: C programming(float) ((VI_H_START_REG.END - VI_H_START_REG.START) * (VI_X_SCALE_REG.ScaleUp / 1024))

Height: C programming(float) (((VI_H_START_REG.END - VI_H_START_REG.START) >> 1) * (VI_X_SCALE_REG.ScaleUp / 1024))

60 Frames per second in Low Resolution mode

This is the easiest mode to use if your frame processing time is very low, because you simply swap the frame buffer 60 times per second inside the VI Interrupt, no other register changes are needed.

Letter Boxing

This is a fairly common effect that is nice for cut scenes or to indicate overworld vs a level.

VI_V_START_REG

Pillar Boxing

This feature is almost the default now since the N64 is intended for a 4:3 screen but is commonly played on 16:9 ratio screens.

VI_H_START_REG

Reduce both Height and Width

Reducing the display size by just a few pixels also reduces the size of the world view that the player has, while usually improving performance. Especially if the purpose of this is to improve performance I recommend doing it in increments of 8 pixels, for example either 4 or 8 pixels off each side and my increasing the size of the player status bars at either the top or bottom of the screen can also reduce the number of objects to draw on the screen.

Use the same techniques mentioned above for Letter Boxing and Pillar Boxing.

Advanced version of this is to reduce either the height or width and to increase the scaling so it still fits the screen but stretches the image out to fill the screen.