Video DAC: Difference between revisions
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The Video DAC is a chip – VDC-NUS, DENC-NUS, AVDC-NUS, or MAV-NUS depending on mainboard revision – that converts the 7-bit-wide synchronous [[Video Interface]] output to analog video. |
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The video DAC is connected to the RCP over a video bus. |
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The Video Interface (VI) sends data to the video DAC from the framebuffer. |
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The video bus is one (7-bit) byte wide and also has a !DSYNC signal. |
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The !DSYNC signal is active on the first out of four bytes. |
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The bus comes out of the RCP and is fed into the video DAC. |
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A clock signal (about 50Mhz) is also connected to the DAC. |
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Only NTSC supports s-video. |
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The control deck can be modified to suport RGB as this was left unconnected in the retail. |
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Only the earlier revision's VDC-NUS uses an external chip (ENC-NUS) to convert RGB to S-Video and composite; instead the latter three DAC chips natively generate S-Video and composite. |
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=== Pinout: === |
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The Video DAC clock runs at 4 times the speed of the pixel clock so that the multiplexing can happen on the VI bus. This allows four sequential VI clocks to be combined to hold a single 21-bit color value for each emitted pixel. Since there are three unused bits in the multiplex sequence, it is unclear why the DAC has only 7 bits of precision instead of 8, and no documentation already found explains this. |
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<nowiki> ---------- -------- |
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[[File:N64videosys.png|thumb|Video DAC Bus and waveform. Image from: http://members.optusnet.com.au/eviltim/n64rgb/n64rgb.html]] |
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| | | | |
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| D0|--------| | composite video |
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This 4 clock process outputs the RGB colors and the VSync, Hsync, Clamp and Csync and is restarted every time !DSync is low. |
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| D1|--------| |---------------- |
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| D2|--------| | |
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The Video Interface relies on being able to send control signals (VSync, HSync, "clamp"=colorburst, CSync) every VI clock during blanking by keeping the !DSYNC input low for multiple clocks in a row. |
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| RCP D3|--------| DAC | luma (s-video) |
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| D4|--------| |---------------- |
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The video clock is provided by one of the two MX8330s (IC U7). |
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| D5|--------| | |
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{| class="wikitable" |
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| D6|--------| | chroma (s-video) |
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|+ |
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| !DSYNC|--------| |---------------- |
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! !DSYNC |
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| clock|---+----| | |
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!LOW |
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| | | | | |
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!high |
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---------- | -------- |
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!high |
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| |
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!high |
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OSC (~50Mhz) |
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|- |
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</nowiki> |
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! stage |
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|Cycle 0 |
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|Cycle 1 |
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|Cycle 2 |
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|Cycle 3 |
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|- |
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|D0 |
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|!Csync |
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|Red 0 |
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|Green 0 |
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|Blue 0 |
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|- |
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|D1 |
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|!Hsync |
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|Red 1 |
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|Green 1 |
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|Blue 1 |
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|- |
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|D2 |
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|!Clamp |
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|Red 2 |
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|Green 2 |
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|Blue 2 |
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|- |
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|D3 |
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|!Vsync |
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|Red 3 |
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|Green 3 |
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|Blue 3 |
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|- |
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|D4 |
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|NA |
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|Red 4 |
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|Green 4 |
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|Blue 4 |
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|- |
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|D5 |
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|NA |
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|Red 5 |
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|Green 5 |
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|Blue 5 |
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|- |
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|D6 |
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|NA |
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|Red 6 |
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|Green 6 |
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|Blue 6 |
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|} |
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There are 3 different video clocks that are used in the N64 for the 3 TV standards: <gallery> |
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File:MX8330 video maths.png|Mx8330 video clock maths and fselect |
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</gallery> |
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{| class="wikitable" |
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|+ |
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!TV Signal Type |
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!MX8330 Nominal input clock (by definition) |
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!MX8330 FSEL input |
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!Clock Maths using datasheet |
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!Resulting nominal frequency |
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|- |
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|NTSC |
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|14.32MHz (18 × 227.5 ÷ 286) |
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|HIGH |
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|(14.3 * 17) / 5 |
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|48.681818 MHz ± 30 ppm |
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|- |
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|PAL |
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|17734475 Hz |
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|LOW |
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|(17.7 * 14) / 5 |
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|49.656530 MHz ± 30 ppm |
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|- |
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|MPAL |
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|14.30MHz (18 × 227.25 ÷ 286) |
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|HIGH |
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|(14.3 * 17) / 5 |
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|48.628322 MHz ± 30 ppm |
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|} |
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The [[Audio Interface]] uses this same clock. |
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Latest revision as of 00:03, 24 June 2023
The Video DAC is a chip – VDC-NUS, DENC-NUS, AVDC-NUS, or MAV-NUS depending on mainboard revision – that converts the 7-bit-wide synchronous Video Interface output to analog video.
Only the earlier revision's VDC-NUS uses an external chip (ENC-NUS) to convert RGB to S-Video and composite; instead the latter three DAC chips natively generate S-Video and composite.
The Video DAC clock runs at 4 times the speed of the pixel clock so that the multiplexing can happen on the VI bus. This allows four sequential VI clocks to be combined to hold a single 21-bit color value for each emitted pixel. Since there are three unused bits in the multiplex sequence, it is unclear why the DAC has only 7 bits of precision instead of 8, and no documentation already found explains this.
This 4 clock process outputs the RGB colors and the VSync, Hsync, Clamp and Csync and is restarted every time !DSync is low.
The Video Interface relies on being able to send control signals (VSync, HSync, "clamp"=colorburst, CSync) every VI clock during blanking by keeping the !DSYNC input low for multiple clocks in a row.
The video clock is provided by one of the two MX8330s (IC U7).
| !DSYNC | LOW | high | high | high |
|---|---|---|---|---|
| stage | Cycle 0 | Cycle 1 | Cycle 2 | Cycle 3 |
| D0 | !Csync | Red 0 | Green 0 | Blue 0 |
| D1 | !Hsync | Red 1 | Green 1 | Blue 1 |
| D2 | !Clamp | Red 2 | Green 2 | Blue 2 |
| D3 | !Vsync | Red 3 | Green 3 | Blue 3 |
| D4 | NA | Red 4 | Green 4 | Blue 4 |
| D5 | NA | Red 5 | Green 5 | Blue 5 |
| D6 | NA | Red 6 | Green 6 | Blue 6 |
There are 3 different video clocks that are used in the N64 for the 3 TV standards:
-
Mx8330 video clock maths and fselect
| TV Signal Type | MX8330 Nominal input clock (by definition) | MX8330 FSEL input | Clock Maths using datasheet | Resulting nominal frequency |
|---|---|---|---|---|
| NTSC | 14.32MHz (18 × 227.5 ÷ 286) | HIGH | (14.3 * 17) / 5 | 48.681818 MHz ± 30 ppm |
| PAL | 17734475 Hz | LOW | (17.7 * 14) / 5 | 49.656530 MHz ± 30 ppm |
| MPAL | 14.30MHz (18 × 227.25 ÷ 286) | HIGH | (14.3 * 17) / 5 | 48.628322 MHz ± 30 ppm |
The Audio Interface uses this same clock.