Video DAC

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The Video DAC is a chip – VDC-NUS, DENC-NUS, AVDC-NUS, or MAV-NUS depending on mainboard revision – that converts the 7-bit-wide synchronous Video Interface output to analog video.

Only the earlier revision's VDC-NUS uses an external chip (ENC-NUS) to convert RGB to S-Video and composite; instead the latter three DAC chips natively generate S-Video and composite.

The Video DAC clock runs at 4 times the speed of the pixel clock so that the multiplexing can happen on the VI bus. This allows four sequential VI clocks to be combined to hold a single 21-bit color value for each emitted pixel. Since there are three unused bits in the multiplex sequence, it is unclear why the DAC has only 7 bits of precision instead of 8, and no documentation already found explains this.

Video DAC Bus and waveform. Image from:

This 4 clock process outputs the RGB colors and the VSync, Hsync, Clamp and Csync and is restarted every time !DSync is low.

The Video Interface relies on being able to send control signals (VSync, HSync, "clamp"=colorburst, CSync) every VI clock during blanking by keeping the !DSYNC input low for multiple clocks in a row.

The video clock is provided by one of the two MX8330s (IC U7).

!DSYNC LOW high high high
stage Cycle 0 Cycle 1 Cycle 2 Cycle 3
D0 !Csync Red 0 Green 0 Blue 0
D1 !Hsync Red 1 Green 1 Blue 1
D2 !Clamp Red 2 Green 2 Blue 2
D3 !Vsync Red 3 Green 3 Blue 3
D4 NA Red 4 Green 4 Blue 4
D5 NA Red 5 Green 5 Blue 5
D6 NA Red 6 Green 6 Blue 6

There are 3 different video clocks that are used in the N64 for the 3 TV standards:

TV Signal Type MX8330 Nominal input clock (by definition) MX8330 FSEL input Clock Maths using datasheet Resulting nominal frequency
NTSC 14.32MHz (18 × 227.5 ÷ 286) HIGH (14.3 * 17) / 5 48.681818 MHz ± 30 ppm
PAL 17734475 Hz LOW (17.7 * 14) / 5 49.656530 MHz ± 30 ppm
MPAL 14.30MHz (18 × 227.25 ÷ 286) HIGH (14.3 * 17) / 5 48.628322 MHz ± 30 ppm

The Audio Interface uses this same clock.