RDRAM: Difference between revisions
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typo in RDRAM_DELAY_REG value
Spacebeans (talk | contribs) m (→RDRAM registers: warps -> wraps) |
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Before we can do anything else at all, we need to somehow set the WriteDelay to the correct value of 001b, despite the fact the WregB command results in the Rambus device reading garbage. <Br>IPL3 gets around this problem by using MI's Repeat mode (called "Init mode" in some documentation), see [[MIPS_Interface#0x0430_0000_-_MI_MODE|MI_MODE]] for more details about MI's various modes.
By configuring a 16 byte repeat (<code>MI_MODE_REG] = 0x10f</code>), the next word written to an Rambus device register (or memory) will be repeated over 16 bytes. This causes RI to emit a 128bit burst request, with the data on the bus during TCycle 4-11. As the Rambus device is sampling the bus during TCycle 7 and 8, it will get valid data we control. <Br>But it's reading data halfway between two words. So IPL3 has to rotate the value by 16 bits to get the correct result. It wants to write <code>0x2838_1808</code>, but it actually writes <code>[0xA3F80000 + RDRAM_DELAY_REG] =
After updating WriteDelay with a broadcast write to all device, all future operations will have the correct timings.
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