RDRAM: Difference between revisions

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100 bytes removed ,  7 months ago
Change register section headings, as MediaWiki really hates linking to anchors with square brackets in them.
m (fix copypasta)
(Change register section headings, as MediaWiki really hates linking to anchors with square brackets in them.)
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TODO: detailed register description, with bit layout and arrows.
 
==== <span style="display:none;">AdrS[9:2] 0x00 - DeviceType ====
----
{{#invoke:Register table|head|600px|DeviceType <code>0x00</code>}}
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}}
 
==== <span style="display:none;">AdrS[9:2] 0x01 - DeviceId ====
----
{{#invoke:Register table|head|600px|DeviceId <code>0x01</code>}}
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}}
 
==== <span style="display:none;">AdrS[9:2] 0x02 - Delay ====
----
{{#invoke:Register table|head|600px|Delay <code>0x02</code>}}
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''<sup>[1]</sup> The Toshiba 8Mbit datasheet confirms this as the default. It default to 4, because some devices (like the Toshiba 18Mbit) only have 2 bits, so can only support a maximum write delay of 4. Devices with more bits default to 0b100 for compatibility.''
 
==== <span style="display:none;">AdrS[9:2] 0x03 - Mode ====
----
{{#invoke:Register table|head|600px|Mode <code>0x03</code>}}
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}}
 
==== <span style="display:none;">AdrS[9:2] 0x04 - RefInterval ====
----
{{#invoke:Register table|head|600px|RefInterval <code>0x04</code>}}
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}}
 
==== <span style="display:none;">AdrS[9:2] 0x05 - RefRow ====
----
{{#invoke:Register table|head|600px|RefRow <code>0x05</code>}}
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This register is normally read or written only for testing purpose.
 
==== <span style="display:none;">AdrS[9:2] 0x06 - RasInterval ====
----
{{#invoke:Register table|head|600px|RasInterval <code>0x06</code>}}
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NOTE: all fields are in bit reversed order (bit 4 is LSB, bit 0 is MSB).
 
==== <span style="display:none;">AdrS[9:2] 0x07 - MinInterval ====
----
{{#invoke:Register table|head|600px|MinInterval <code>0x07</code>}}
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''The N64 implements refresh by broadcasting one SetRR command whenever VI emits a horizontal sync pulse.''
 
==== <span style="display:none;">AdrS[9:2] 0x08 - AddressSelect ====
----
{{#invoke:Register table|head|600px| AddressSelect <code>0x08</code>}}
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: However, RI doesn't appear to support this feature. It expects Bank zero to be in the first megabyte of address space, Bank one in the second megabyte, and so on.
 
==== <span style="display:none;">AdrS[9:2] 0x09 - DeviceManufacturer ====
----
{{#invoke:Register table|head|600px| DeviceManufacturer <code>0x09</code>}}
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