RDRAM: Difference between revisions
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Document CAS timing values meaning (in tcycles)
m (Fix CAS timings used in IPL3) |
m (Document CAS timing values meaning (in tcycles)) |
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Line 318:
{{#invoke:Register table|head|600px|Delay <code>0x02</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || RW-
|-
| — || — || colspan="3" | AckWinDelay || colspan="3" | AckWinBits
Line 335:
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 29-27 | AckWinDelay[2:0] | Adjusts the size of the acknowledge window. Normally set to 5 {{=}} 101b.<br>101b {{=}} 5 tcycles<br>110b {{=}} 6 tcycles<br>111b {{=}} 7 tcycles<br>000b {{=}} 8 tcycles<br>001b {{=}} 9 tcycles<br>010b {{=}} 10 tcycles<br>011b {{=}} 11 tcycles<br>100b {{=}} 12 tcycles
| 26-24 | AckWinBits[2:0] | Read-only. Number of bits of AckWinDelay (3).
| 21-19 | ReadDelay[2:0] | Delay between end of request and start of Read data packet. Normally set to 7 {{=}} 111b.<br>111b {{=}} 7 tcycles<br>000b {{=}} 8 tcycles<br>001b {{=}} 9 tcycles<br>010b {{=}} 10 tcycles<br>011b {{=}} 11 tcycles<br>100b {{=}} 12 tcycles<br>101b {{=}} 13 tcycles<br>110b {{=}} 14 tcycles
| 18-16 | ReadBits[2:0] | Read-only. Number of bits of ReadDelay (3).
| 12-11 | AckDelay[1:0] | Delay between end of request and start of Ack data packet. Normally set to 3 {{=}} 11b.<br>11b {{=}} 3 tcycles<br>00b {{=}} 4 tcycles<br>01b {{=}} 5 tcycles<br>10b {{=}} 6 tcycles
| 10-8 | AckBits[2:0] | Read-only. Number of bits of AckDelay (2).
| 5-3 | WriteDelay[2:0] | Delay between end of request and start of Write data packet. Normally set to 1 {{=}} 001b.<br>001b {{=}} 1 tcycles<br>010b {{=}} 2 tcycles<br>011b {{=}} 3 tcycles<br>100b {{=}} 4 tcycles<br>101b {{=}} 5 tcycles<br>110b {{=}} 6 tcycles<br>111b {{=}} 7 tcycles<br>000b {{=}} 8 tcycles
| 2-0 | WriteBits[2:0] | Read-only. Number of bits of WriteDelay (3).
}}
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