RDRAM: Difference between revisions

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RDRAM (view source)

Revision as of 20:26, 24 September 2023

207 bytes removed ,  9 months ago
Fix bits ordering in RDRAM registers layout.
VisualWikitext
(Fix bits ordering in RDRAM registers layout.)
Line 253:
Programming caution :
 
* RDRAM registers are '''little-endian'''. The RI does not perform any endian-swap, so the value that is read or written by the CPU '''must be endian-swapped''' to match the register layout described in this page.
* Before reading any RDRAM register content, RDRAM current control must be calibrated
* Also, it seems that RDRAM register reads should be surrounded by MI_MODE = SET_DRAM_REG / CLR_DRAM_REG
Line 265 ⟶ 264:
{{#invoke:Register table|head|600px|DeviceType <code>0x00</code>}}
{{#invoke:Register table|row|31:24}}
| R-0? || R-0? || R-0? || R-? || RU-0 || R-01 || RU-0 || R-0?
|-
| colspan="4" | VersionColumnBits || colspan="4"— || Bn || — || TypeEn
{{#invoke:Register table|row|23:16}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0▼
|-▼
| — || — || — || — || — || — || — || —▼
{{#invoke:Register table|row|15:8}}▼
| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
|-
| colspan="4" | BankBits || colspan="4" | RowBits
▲{{#invoke:Register table|row|15:8}}
▲| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
▲|-
▲| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| R-?0 || R-?0 || R-?0 || R-? || UR-0 || R-10 || UR-0 || R-?0
|-
| colspan="4" | ColumnBitsVersion || —colspan="4" || Bn || — || EnType
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 1531-1228 | BankBitsColumnBits | Number of bankcolumn address bits, or said differently, declares that this RDRAM device has 2^BankBitsColumnBits banksbytes per row.▼
| 31-28 | Version | RDRAM version. <br>0001 {{=}} Extended architecture (Base RDRAM protocol)
| 27-2426 | TypeBn | DeviceBonus, typenumber of bits per byte. <br>00000 {{=}} 8bit byte<br>1 {{=}} RDRAM9bit devicebyte
| 24 | En | Enhanced speed grade. <br>0 {{=}} Normal<br> 1 {{=}} Low Latency
▲| 15-12 | BankBits | Number of bank address bits, or said differently, declares that this RDRAM device has 2^BankBits banks.
| 1123-820 | RowBitsBankBits | Number of rowbank address bits, or said differently, declares that this RDRAM devicesdevice has 2^RowBitsBankBits rows per bankbanks.
| 719-416 | ColumnBitsRowBits | Number of columnrow address bits, or said differently, declares that this RDRAM devicedevices has 2^ColumnBitsRowBits bytesrows per rowbank.
| 27-4 | BnVersion | Bonus,RDRAM number of bits per byteversion. <br>00001 {{=}} 8bitExtended byte<br>1architecture {{=}}(Base 9bitRDRAM byteprotocol)
| 3-0 | EnType | EnhancedDevice speed gradetype. <br>0 {{=}} Normal<br> 10000 {{=}} LowRDRAM Latencydevice
}}
 
Line 295 ⟶ 294:
{{#invoke:Register table|head|600px|DeviceId <code>0x01</code>}}
{{#invoke:Register table|row|31:24}}
| RW-0 || URW-0 || URW-0 || URW-0 || URW-0 || U-0 || U-0 || U-0
|-
| colspan="5" | IdField[3525:20] || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| RW-10 || RWU-10 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0▼
|-▼
| C4IdField[26] || C1— || — || — || — || — || — || —▼
{{#invoke:Register table|row|15:8}}▼
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | IdField[34:27]
{{#invoke:Register table|row|157:80}}
| RW-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| IdField[2635] || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0 || U-0
▲|-
| colspan="5" | IdField[25:20] || — || — || —
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 317,2315-168,1523,731-326 | IdField[35:k] | Compared to AdrS[35:k] to select RDRAM.<br>k {{=}} 21 for 16/18Mbit RDRAM.<br>k {{=}} 20 for 8/9Mbit RDRAM.
}}
 
Line 321 ⟶ 320:
{{#invoke:Register table|head|600px|Mode <code>0x03</code>}}
{{#invoke:Register table|row|31:24}}
| RW-1 || RW-1 || URW-0 || UR-0 || URW-0 || URW-01 || URW-0 || URW-0
|-
| C3CE || C0X2 || —PL || —SV || —SK || —AS || —DE || —LE
{{#invoke:Register table|row|23:16}}
▲| RW-1 || RW-1 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-▼
▲| C4 || C1 || — || — || — || — || — || —
▲{{#invoke:Register table|row|15:8}}
| RW-1 || RW-1 || U-0 || U-0 || RW-0 || U-0 || U-0 || U-0
|-
| C5 || C2 || — || — || AD || — || — || —
▲{{#invoke:Register table|row|715:08}}
▲| RW-01 || RW-01 || RWU-0 || RWU-0 || RWU-0 || U-0 || U-0 || U-0
▲|-
| C4 || C1 || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| RW-1 || RW-1 || RWU-0 || RU-0 || RWU-0 || RWU-10 || RWU-0 || RWU-0
|-
| CEC3 || X2C0 || PL— || SV— || SK— || AS— || DE— || LE—
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 731 | CE / CCEnable| Current Control Enable.<br>0 {{=}} manual<br>1 {{=}} auto▼
| 15,23,31,14,22,30 | C[5:0] / CCValue | Current Control value which controls ''in fine'' the output current I<sub>OL</sub>.<br>In manual mode (CE{{=}}0), I<sub>OL</sub> is proportional to (63-CC) with I<sub>OL</sub> ~ (0.95±0.3)×(63-CC) mA, for CC {{=}} 0..63. (These coefficients derive from Imax±△/63 and vary between models)<br>This field is inverted when read.<br>In auto mode (CE{{=}}1), I<sub>OL</sub> is proportional to (63-CC) with I<sub>OL</sub> ~ (1.25±0.1)×(63-CC) mA, for CC {{=}} 31..63. (These coefficients derive from I<sub>40</sub>±△/(63-31) and vary between models)<br>An internally generated value is returned when read.▼
| 630 | X2 / CCMult | Should be 1. Inverted when read. (Toshiba datasheet states that it select wether X<sub>1</sub> or X<sub>2</sub> register is used for the current control register).▼
| 11 | AD / AckDis | For low latency RDRAM only. Allows to supress acknowledge response when set to 1.▼
| 29 | PL | Select PowerDown Latency
▲| 7 | CE / CCEnable| Current Control Enable.<br>0 {{=}} manual<br>1 {{=}} auto
| 328 | SKSV / SkipSkipValue | For tests. 0▼
▲| 6 | X2 / CCMult | Should be 1. Inverted when read. (Toshiba datasheet states that it select wether X<sub>1</sub> or X<sub>2</sub> register is used for the current control register).
| 527 | PLSK / Skip| SelectFor PowerDowntests. Latency0
| 426 | SVAS / SkipValueAutoSkip | For tests. 01
| 125 | DE / DeviceEnable | Enable RDRAM device. When disabled, only broadcast register requests can be executed.<br>0 {{=}} disabled<br>1 {{=}} enabled▼
▲| 3 | SK / Skip| For tests. 0
| 024 | LE | Enable PowerDown mode for RDRAM that supports it to reduce power consumption.▼
| 2 | AS / AutoSkip | For tests. 1
▲| 1119 | AD / AckDis | For low latency RDRAM only. Allows to supress acknowledge response when set to 1.
▲| 1 | DE / DeviceEnable | Enable RDRAM device. When disabled, only broadcast register requests can be executed.<br>0 {{=}} disabled<br>1 {{=}} enabled
▲| 15,23,3115,147,22,3014,6 | C[5:0] / CCValue | Current Control value which controls ''in fine'' the output current I<sub>OL</sub>.<br>In manual mode (CE{{=}}0), I<sub>OL</sub> is proportional to (63-CC) with I<sub>OL</sub> ~ (0.95±0.3)×(63-CC) mA, for CC {{=}} 0..63. (These coefficients derive from Imax±△/63 and vary between models)<br>This field is inverted when read.<br>In auto mode (CE{{=}}1), I<sub>OL</sub> is proportional to (63-CC) with I<sub>OL</sub> ~ (1.25±0.1)×(63-CC) mA, for CC {{=}} 31..63. (These coefficients derive from I<sub>40</sub>±△/(63-31) and vary between models)<br>An internally generated value is returned when read.
▲| 0 | LE | Enable PowerDown mode for RDRAM that supports it to reduce power consumption.
}}
 
Bsmiles32
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