Memory map: Difference between revisions
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== Physical Memory Map ==
{| class="wikitable"
!Bus / Device
! colspan=2 | Address Range !! Name !! Description
|-
| rowspan="2" |RDRAM
| 0x00000000 || 0x003FFFFF || RDRAM || RDRAM located on motherboard
|-
| 0x00400000 || 0x007FFFFF || RDRAM || RDRAM from [[Expansion Pak]] (if present)
|-
|?
| 0x00800000 || 0x03EFFFFF || Reserved || Unknown usage
|-
| rowspan="14" |RCP
| 0x03F00000 || 0x03FFFFFF || [[RDRAM#Registers|RDRAM Registers]]|| RDRAM configuration registers
|-
Line 58 ⟶ 62:
| 0x04900000 || 0x04FFFFFF || Unused || Unused
|-
| rowspan="4" |PI external bus
| 0x05000000 || 0x05FFFFFF || Cartridge Domain 2 Address 1 || N64DD control registers (if present)
|-
Line 66 ⟶ 71:
| 0x10000000 || 0x1FBFFFFF || Cartridge Domain 1 Address 2 || [[ROM Header|Cartridge ROM]]
|-
| rowspan="3" |SI external bus
| 0x1FC00000 || 0x1FC007BF || PIF ROM ([[Initial Program Load|IPL1/2]]) || Executed on boot
|-
Line 72 ⟶ 78:
| 0x1FC00800 || 0x1FCFFFFF || Reserved || Unknown usage
|-
|PI external bus
| 0x1FD00000 || 0x7FFFFFFF || Cartridge Domain 1 Address 3 || Mapped to same address range on physical cartridge port
|-
|
| 0x80000000 || 0xFFFFFFFF || Unmapped || Unmapped area
|}
Cartridge Domains 1 and 2 are mapped one-to-one on the cartridge/bottom port. It is not known at this time what Domain 1 Address 3 was used for, if at all, but flash carts may have some use for that address range.
Line 99 ⟶ 107:
* Writes: RCP will ignore the requested access size and just write the word that was put on the bus directly into the hardware register. For 8-bit and 16-bit accesses, this means that the shifted value prepared by the VR4300 is the one that will be written verbatim. Reprising the example above, if <code>S0=0x1234'5678</code>, <code>A0=0x0460'0011</code>, running <code>SB S0, 0(A0)</code> will write the value <code>0x5678'0000</code> to the RCP hardware register <code>0x0460'0010</code>. For 64-bit accesses, as they are written on the bus MSB-first, the RCP will write the MSB to the hardware register, ignoring the LSB.
=== Range 0x1FC0'0000 - 0x1FCF'FFFF (
TODO
===
All accesses made by the VR4300 in these ranges are forward externally by RCP on the external PI bus. This allows the CPU to access external devices connected to the parallel bus like the cartridge ROM and SRAM.
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