Serial Interface
The Serial Interface (or SI) is one of multiple I/O interfaces in the RCP, which is used to communicate with the PIF-NUS and in turn, Joybus devices.
Memory mapped registers are used to configure the Serial Interface and initiate DMA reads and writes. The base address for these registers is 0x0480 0000, also known as SI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add 0xA000 0000 to the address. As an example, to directly write to the SI_DRAM_ADDR register, use address 0xA480 0000.
Registers
Table Notation:
R = Readable bit W = Writable bit U = Undefined/Unused bit -n = Default value n at power on [x:y] = Specifies bits x to y, inclusively
SI_DRAM_ADDR 0x0440 0000
| ||||||||
|---|---|---|---|---|---|---|---|---|
| 31:24 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 |
| — | — | — | — | — | — | — | — | |
| 23:16 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
| DRAM_ADDR[23:16] | ||||||||
| 15:8 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
| DRAM_ADDR[15:8] | ||||||||
| 7:0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
| DRAM_ADDR[7:0] | ||||||||
| bit 31-24 | Undefined: Initialized to 0
|
| bit 23-0 | DRAM_ADDR[23:0]: RDRAM address used in SI DMAs |
SI_PIF_AD_RD64B 0x0440 0004
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TODO
SI_PIF_AD_WR4B 0x0440 0008
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|---|
TODO
SI_PIF_AD_WR64B 0x0440 0010
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TODO
SI_PIF_AD_RD4B 0x0440 0014
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TODO
SI_STATUS 0x0440 0018
| ||||||||
|---|---|---|---|---|---|---|---|---|
| 31:24 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 |
| — | — | — | — | — | — | — | — | |
| 23:16 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 |
| — | — | — | — | — | — | — | — | |
| 15:8 | U-0 | U-0 | U-0 | R-0 | U-0 | U-0 | U-0 | U-0 |
| — | — | — | INTERRUPT | DMA_STATE[3:0] | ||||
| 7:0 | U-0 | U-0 | U-0 | U-0 | R-0 | R-0 | R-0 | R-0 |
| PCH_STATE[3:0] | DMA_ERROR | READ_PENDING | IO_BUSY | DMA_BUSY | ||||
| bit 31-13 | Undefined: Initialized to 0
|
| bit 12 | INTERRUPT: Copy of SI interrupt flag from MIPS Interface, which is also seen in the RCP Interrupt Cause register. Writing any value to SI_STATUS clears this bit in all three locations. SI interrupts occur when either a DMA or IO write finishes. |
| bit 11-8 | DMA_STATE[3:0]: Internal-only (likely not readable). Non-zero values indicate activity. |
| bit 7-4 | PCH_STATE[3:0]: Internal-only (likely not readable). Non-zero values indicate activity. |
| bit 3 | DMA_ERROR: Set when overlapping DMA requests occur. Can only be cleared with a power reset. |
| bit 2 | READ_PENDING: Set when an IO read occurs, while an IO or DMA write is in progress. |
| bit 1 | IO_BUSY: Set when either an IO read or write is in progress. |
| bit 0 | DMA_BUSY: Set when a read or write DMA, or an IO write, is in progress. |