Reality Signal Processor

The Reality Signal Processor, or RSP, is the portion of the RCP responsible for matrix math, lighting calculations, clipping, shading, and other highly parallel graphics tasks as well as audio processing.

It is made by a stripped-down MIPS 32-bit core (without a few more advanced opcodes) referred to as Scalar Unit (SU), composed with a coprocessor (configured as COP2) that can perform SIMD operations on a separate set of vector registers, referred to as Vector Unit (VU).

RSP has two different banks of onboard dedicated memories: IMEM (4KB) for instructions, and DMEM (4KB) for data. It has no external memory buses but has a DMA engine capable to copy code/data from/into DMEM/IMEM and the main RDRAM. The DMA engine can be driven by either the main CPU or the RSP itself.

Specs

	Discription
CPU Type	Cut down version of the MIPS4000 CPU
Clock Speed	62.5mhz
Instruction Size	32bit (1 Word)
Duel Instruction	Yes (one scaler and one vector opcode at once)
Pipeline Stages	5 stage pipeline for both the Scaler and Vector Pipelines IF, RD and WB stages are shared between the two pipelines
IMEM Data Path	64bit (This allows a duel instruction to happen) This can only be double word aligned for reads
Scaler Register Size	32 entries of 32bit in size (Word Writable)
Vector Register Size	32 entries of 128bit is size (8bit to 128bit Mask Writable File)
DMEM Scaler Data Path	Up to 32bit Loads and Stores
DMEM Vector Data Path	Up to 128bit Loads and Stores
Scaler ALU Size	32bit in side only
Vector ALU Size	8x 16bit vector ALU pipelines (48bit Final Accumulator)

RSP CPU core

The code running on the RSP is usually called "microcode", but it's a standard MIPS program, obviously containing the dedicated COP2 instructions to drive the VU. The RSP can be programmed in custom microcode to handle specific tasks, though most commercial games leveraged one of several stock microcodes made available by Nintendo at the time.