Reality Signal Processor/CPU Core: Difference between revisions
→128-bit vector loads: LQV, LRV
(→Usage) |
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===== Assembly =====
<syntaxhighlight lang="asm">
// Standard 128-bit load from DMEM aligned address s0 into $v08
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(→Usage) |
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Line 719:
|}
===== Assembly =====
<syntaxhighlight lang="asm">
// Standard 128-bit load from DMEM aligned address s0 into $v08
| |||