Reality Signal Processor/CPU Core: Difference between revisions
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Spacebeans (talk | contribs) m (A few value corrections) |
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!Description |
!Description |
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|0x20 |
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|0x00 |
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|<code>vlt</code> |
|<code>vlt</code> |
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|Select the lower value between two VPR |
|Select the lower value between two VPR |
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|0x21 |
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|0x01 |
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|<code>veq</code> |
|<code>veq</code> |
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|Compare two VPR to check if they are equal |
|Compare two VPR to check if they are equal |
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|0x22 |
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|0x02 |
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|<code>vne</code> |
|<code>vne</code> |
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|Compare two VPR to check if they are different |
|Compare two VPR to check if they are different |
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|- |
|- |
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|0x23 |
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|0x03 |
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|<code>vge</code> |
|<code>vge</code> |
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|Select the greater or equal value between two VPR |
|Select the greater or equal value between two VPR |
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|- |
|- |
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|0x24 |
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|0x04 |
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|<code>vcl</code> |
|<code>vcl</code> |
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|Clip a VPR against two bounds (lower 16-bits) |
|Clip a VPR against two bounds (lower 16-bits) |
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|- |
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|0x25 |
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|0x05 |
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|<code>vch</code> |
|<code>vch</code> |
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|Clip a VPR against two bounds (higher 16-bits) |
|Clip a VPR against two bounds (higher 16-bits) |
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|- |
|- |
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|0x26 |
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|0x06 |
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|<code>vcr</code> |
|<code>vcr</code> |
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|Clip a VPR against a pow-2 bound |
|Clip a VPR against a pow-2 bound |
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|- |
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|0x27 |
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|0x07 |
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|<code>vmrg</code> |
|<code>vmrg</code> |
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|Merge two VPR selecting each lane according to flags |
|Merge two VPR selecting each lane according to flags |
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<code>mtc2</code> moves the lower 16 bits of the general purpose register <code>rt</code> to the bytes <code>VS[vs_elem+1..vs_elem]</code>. If <code>vs_elem</code> is 15, only <code>VS[vs_elem]</code> is written (with <code>rt[15..8]</code>). |
<code>mtc2</code> moves the lower 16 bits of the general purpose register <code>rt</code> to the bytes <code>VS[vs_elem+1..vs_elem]</code>. If <code>vs_elem</code> is 15, only <code>VS[vs_elem]</code> is written (with <code>rt[15..8]</code>). |
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<code>mfc2</code> moves the 2 bytes <code>VS[vs_elem+1..vs_elem]</code> to GPR <code>rt</code>, sign extending the 16 bits value to |
<code>mfc2</code> moves the 2 bytes <code>VS[vs_elem+1..vs_elem]</code> to GPR <code>rt</code>, sign extending the 16 bits value to 32 bits. If <code>vs_elem</code> is 15, the lower byte is taken from byte 0 of the register (that is, it wraps around). |
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<code>ctc2</code> moves the lower 16 bits of GPR <code>rt</code> into the control register specified by <code>vs</code>, while <code>cfc2</code> does the reverse, moving the control register specified by <code>vs</code> into GPR <code>rt</code>, sign extending to |
<code>ctc2</code> moves the lower 16 bits of GPR <code>rt</code> into the control register specified by <code>vs</code>, while <code>cfc2</code> does the reverse, moving the control register specified by <code>vs</code> into GPR <code>rt</code>, sign extending to 32 bits. Note that both <code>ctc2</code> and <code>cfc2</code> ignore the <code>vs_elem</code> field. For these instructions, the control register is specified as follows: |
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{| class="wikitable" |
{| class="wikitable" |
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!<code>vs</code> |
!<code>vs</code> |