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RDRAM Interface (view source)

Revision as of 23:36, 1 September 2021

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Verified the RI contains a RAC, and clarified which specific registers were defined on this page.
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(Verified the RI contains a RAC, and clarified which specific registers were defined on this page.)
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The RDRAM Interface (or '''RI''') actis one of multiple I/O interfaces in the RCP. It acts as a controller offor the RDRAM channel to which one or more RDRAM modules are connected. It converts memory accesses from the system into RDRAM protocol commands, tofor whichthe RDRAM modules respondsbus. The RI very likely integrates a RDRAM ASIC Cell (or '''RAC''') in order to take care of the low level details of the RDRAM bus. Further details about such a RAC can be found in datasheets like [https://www.datasheetarchive.com/pdf/download.php?id=04f8a219efa5e2304d0e403c3f77e759adedf8&type=O&term=rac%2520rdram thisdatasheets onefor similar RACs] (even if it mayhowever not benecessarily the very same version used inby the official RIN64).
 
There are two sets of memory mapped registers for RDRAM configuration. One set is specifically for writing to or reading from the configuration registers in one or all individual [[RDRAM]] module(s). The other set, defined in the next section, configure this RDRAM interface. Refer to [[Memory map]] for the full map, including all RDRAM-related segments.
The memory area devoted to RDRAM Interface and RDRAM modules is divided as follow :
{| class="wikitable"
|+memory area devoted to RDRAM Interface and modules
! colspan="2" |Address Range
!Name
!Description
|-
|<code>0x0000 0000</code>
|<code>0x03EF FFFF</code>
|RDRAM memory
|Allows to access RDRAM memory of configured module
|-
|<code>0x03F0 0000</code>
|<code>0x03FF FFFF</code>
|RDRAM registers
|Allows to access RDRAM register of configured module
|-
|<code>0x0470 0000</code>
|<code>0x047F FFFF</code>
|RI registers
|Allows to configure RDRAM Interface behavior
|}
 
The base address for these registers is <code>0x0470 0000</code>, also known as RI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add <code>0xA000 0000</code> to the address. As an example, to directly write to the RI_MODE register, use address <code>0xA470 0000</code>.
== Registers ==▼
 
▲== Registers ==
'''Table Notation:'''
<pre>
R = Readable bit
W = Writable bit
U = Undefined/Unused bit
-n = Default value n at power on
[x:y] = Specifies bits x to y, inclusively</pre>
==== <span style="display:none;">0x0470 0000 - RI_MODE ====
----
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