RDRAM Interface: Difference between revisions
Tentative description of RDRAM address mapping
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(Tentative description of RDRAM address mapping) |
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TODO: remaining registers
== Memory addressing ==
RI translate memory accesses in the range <code>0x0000 0000</code> - <code>0x03FF FFFF</code> into suitable RDRAM protocol packets with proper command type and address (36bits). Typical commands includes memory reads or writes (there are many different kinds which takes into account wether the access is sequential, random, byte masked, ...), register read, register write and broadcast register write (all connected RDRAM modules are affected).
These packets are then sent on the RDRAM channel where matching RDRAM module (or all in case of a broadcast register write) can act on. We define a matching RDRAM module as follow :
Given a 36bit address Adr[35:0], we compute a "bit-swapped" address AdrS[35:0] such that bits [28:20] and [19:11] are swapped on a bit by bit basis based on the value SwapField from AddressSelect register. The upper 16 bits of AdrS are then compared to the IdField contained in DeviceId register. If they are equal, or if the operation is a Broadcast register write, the RDRAM module has an Id match. Note that for 2x9Mbit modules the lowest of the 16bits is ignored.
More formally this gives:
<code>IdMatch = BCastRWrite || AdrS[35:M] == IdField[35:M]</code>
<code>with AdrS[35:29] = Adr[35:29], AdrS[28:20] = (SwapField[8:0] x Adr[19:11]) + ~SwapField[8:0]xAdr[28:20], AdrS[19:11] = (~SwapField[8:0] x Adr[19:11]) + SwapField[8:0]xAdr[28:20], AdrS[10:0] = Adr[10:0]</code>
<code>and M = 21 for 2x9Mbit modules, M = 20 for 1x9Mbit modules.</code>
Address conversion done by RI (TOVERIFY, earlier version of RCP may have mapped RDRAM registers slightly differently):
{| class="wikitable"
! colspan="2" |Address Range
!Adr[35:20]
!Adr[19:0]
!BCastRWrite
!Description
|-
|<code>0x0000 0000</code>
|<code>0x03EF FFFF</code>
|(address >> 20) & 0x3F
|address & 0xFFFFF
|0
|Memory-space access
|-
|<code>0x03F0 0000</code>
|<code>0x03F7 FFFF</code>
|(address >> 10) & 0x1FF
|address & 0x3FF
|(address >> 19) & 0x1 == 0
|Register-space access
|-
|<code>0x03F8 0000</code>
|<code>0x03FF FFFF</code>
|(address >> 10) & 0x1FF
|address & 0x3FF
|(address >> 19) & 0x1 == 1
|Broadcast register write
|}
Examples :
Assuming a standard RDRAM configuration of 4x2x9Mbit RDRAM each with IdField = 2*k for module k = 0..3 and SwapField = 0 for all modules (eg. no address swapping, Adr = AdrS).
Reading at address 0x003A BCDE, gives the following Adr[35:20] = 3, Adr[19:0] = 0xABCDE, BCastRWrite = 0. Since we have 2x9Mbit modules, Adr[20] is ignored for Id matching and therefore RDRAM with IdField == 2 gives a match. This means RDRAM module 1 will be read at address 0x1abcde.
Writing at address 0x03F0 0808, gives Adr[35:20] = 2, Adr[19:0] = 8, BCastRWrite = 0. Which means writing to RDRAM module 1 delay register.
Writing at address 0x03F8 0008, gives BCastRWrite = 1, Adr[19:0] = 8. Which means broadcast writing to all RDRAM modules delay registers.
Remarks :
- Early version of RCP reserved fewer bits for RDRAM register address (eg. Adr[35:20] = (address >> 9) & 0x3FF; Adr[19:0] = address & 0x1FF) which didn't allow to access RDRAM register 128 (Row register) which is at offset 0x200.
- The presented address map supports up to 32x 2x9Mbit RDRAM modules.
- Standard DRAM initialization only supports up to 8 modules, but can mix 2x9Mbit and 1x9Mbit modules. In that case, 2x9Mbit modules are placed before 1x9Mbit modules.
- Standard DRAM initialization procedure, doesn't make use of address swapping feature, even though it may increase DRAM hit rate according to datasheets.
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