RDRAM Interface: Difference between revisions

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(RI_CONFIG and RI_CURRENT_LOAD: Relate fields to relevant RAC signals, document read behavior for RI_CURRENT_LOAD)
(RI_SELECT: Partial research into the set of allowed configurations)
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{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-8 | Undefined | Undefined
| 31-8 | Undefined | Undefined
| 7-4 | TSEL[3:0] | Configure transmit signals timings. Very likely related to RAC signals B{C,D,E}Sel. Usually set to <code>0x1</code>.
| 7-4 | TSEL[3:0] | Configure transmit signals timings. Corresponds to RAC signals B{C,D,E}Sel.
| 3-0 | RSEL[3:0] | Configure receive signals timings. Very likely related to RAC signal RDSel. Usually set to <code>0x4</code>.
| 3-0 | RSEL[3:0] | Configure receive signals timings. Corresponds to RAC signals R{C,D}Sel.
}}
}}

'''Extra Details:'''
IPL3 configures TSEL to <code>0b0001</code> and RSEL to <code>0b0100</code>. It is currently unclear if this is the only valid configuration.


==== <span style="display:none;">0x0470 0010 - RI_REFRESH ====
==== <span style="display:none;">0x0470 0010 - RI_REFRESH ====
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* Standard DRAM initialization procedure, doesn't make use of address swapping feature, even though it may increase DRAM hit rate according to datasheets.
* Standard DRAM initialization procedure, doesn't make use of address swapping feature, even though it may increase DRAM hit rate according to datasheets.
*Register-space addresses duplicates the content between Adr[28:20] and Adr[19:11] to not be affected by RDRAM address swapping features. Indeed, whereas address swapping is desirable for RDRAM memory to benefit from row internal row caching, registers won't benefit from the swapping and would complicate usage of registers in such a case.
*Register-space addresses duplicates the content between Adr[28:20] and Adr[19:11] to not be affected by RDRAM address swapping features. Indeed, whereas address swapping is desirable for RDRAM memory to benefit from row internal row caching, registers won't benefit from the swapping and would complicate usage of registers in such a case.

= RI_SELECT configurations =

<big>'''Warning: This section contains speculative information that is in need of further research.'''</big>

It is currently unclear what the full set of working configurations for the TSEL and RSEL fields of RI_SELECT are. A datasheet for a Rambus Memory Controller (RMC), a component similar in function to the RI that interfaces with a Rambus ASIC Cell (RAC), refers to the IPL3 configuration (<code>TSEL=0b0001, RSEL=0b0100</code>) as "Option A". The same datasheet mentions an alternative configuration, "Option Z", configured with (<code>TSEL=0b0010, RSEL=0b1000</code>) and considers this configuration preferable over Option A:
{{Blockquote
|text=Option Z is the recommended timing option for the RMC. This minimizes the setup times of all inputs.
|author=RMC datasheet
}}
Option Z has been tested on hardware and does not appear to cause noticeable instability in RDRAM operation, although it is still unclear whether the claim about Option Z being preferable is applicable to the RI. Other "random" configurations for TSEL and RSEL were also attempted but these quickly crashed, however it is still unclear whether the two options mentioned by the RMC datasheet are the extent of possible configurations, and which configuration should be preferred on N64.
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