RDRAM Interface: Difference between revisions

Jump to navigation Jump to search
Content added Content deleted
VisualWikitext
(No idea what DmaLatencyOverlap does, but we do know it's 4 bits.)
m (RI_REFRESH: MultiBank bitfield width is four bits.)
Line 133: Line 133:
| U-? || U-? || U-? || RW-? || RW-? || RW-? || RW-? || RW-?
| U-? || U-? || U-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
|-
| — || — || — || colspan="2" | MultiBank[??:0] || Opt || En || Bank
| — || colspan="4" | MultiBank[3:0] || Opt || En || Bank
{{#invoke:Register table|row|15:8}}
{{#invoke:Register table|row|15:8}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
Line 145: Line 145:
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-?? | Undefined | Undefined
| 31-?? | Undefined | Undefined
| ??-19| MultiBank[??:0] | Bitfield indicating multibanks rdram modules. (Bitfield size to be determined, very likely between 2 and 8). <br>Probably why RDRAM modules are re-ordered with multibanks modules first.
| ??-19| MultiBank[3:0] | Bitfield indicating multibank RDRAM modules. Up to four multibank modules are tracked, enough to fill 8MiB with 4x2MiB modules. <br>Probably why RDRAM modules are re-ordered with multibanks modules first during initialization in IPL3.
| 18 | Opt | Optimize. Usually set to <code>0x1</code>.
| 18 | Opt | Optimize. Usually set to <code>0x1</code>.
| 17 | En | Enable. Usually set to <code>0x1</code>.
| 17 | En | Enable. Usually set to <code>0x1</code>.
Retrieved from "https://n64brew.dev/wiki/RDRAM_Interface"