RDRAM Interface: Difference between revisions
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m (bullet formatting) |
(RI translation does very likely "disable" address swapping for registers operations by duplicating content between Adr[28:20] and Adr[19:11]) |
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{| class="wikitable" |
{| class="wikitable" |
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! colspan="2" |Address Range |
! colspan="2" |Address Range |
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!Adr[35: |
!Adr[35:29] |
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!Adr[ |
!Adr[28:20] |
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!Adr[19:11] |
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!Adr[10:0] |
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!BCastRWrite |
!BCastRWrite |
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!Description |
!Description |
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|<code>0x0000 0000</code> |
|<code>0x0000 0000</code> |
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|<code>0x03EF FFFF</code> |
|<code>0x03EF FFFF</code> |
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|0 |
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|(address >> 20) & 0x3F |
|(address >> 20) & 0x3F |
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|address & |
|(address >> 11) & 0x1FF |
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|address & 0x7FF |
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|0 |
|0 |
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|Memory-space access |
|Memory-space access |
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|<code>0x03F0 0000</code> |
|<code>0x03F0 0000</code> |
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|<code>0x03F7 FFFF</code> |
|<code>0x03F7 FFFF</code> |
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|0 |
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|(address >> 10) & 0x1FF |
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|(address >> 10) & 0x1FF |
|(address >> 10) & 0x1FF |
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|address & 0x3FF |
|address & 0x3FF |
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|<code>0x03F8 0000</code> |
|<code>0x03F8 0000</code> |
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|<code>0x03FF FFFF</code> |
|<code>0x03FF FFFF</code> |
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|0 |
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|(address >> 10) & 0x1FF |
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|(address >> 10) & 0x1FF |
|(address >> 10) & 0x1FF |
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|address & 0x3FF |
|address & 0x3FF |
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|Broadcast register write |
|Broadcast register write |
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|} |
|} |
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Examples : |
Examples : |
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* Standard DRAM initialization only supports up to 8 modules, but can mix 2x9Mbit and 1x9Mbit modules. In that case, 2x9Mbit modules are placed before 1x9Mbit modules. |
* Standard DRAM initialization only supports up to 8 modules, but can mix 2x9Mbit and 1x9Mbit modules. In that case, 2x9Mbit modules are placed before 1x9Mbit modules. |
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* Standard DRAM initialization procedure, doesn't make use of address swapping feature, even though it may increase DRAM hit rate according to datasheets. |
* Standard DRAM initialization procedure, doesn't make use of address swapping feature, even though it may increase DRAM hit rate according to datasheets. |
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*Register-space addresses duplicates the content between Adr[28:20] and Adr[19:11] to not be affected by RDRAM address swapping features. Indeed, whereas address swapping is desirable for RDRAM memory to benefit from row internal row caching, registers won't benefit from the swapping and would complicate usage of registers in such a case. |
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