RDRAM Interface: Difference between revisions
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m (RI_REFRESH: MultiBank bitfield width is four bits.) |
(RI_BANK_STATUS: Further details) |
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{{#invoke:Register table|definitions |
{{#invoke:Register table|definitions |
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| 31-16 | Undefined | Undefined |
| 31-16 | Undefined | Undefined |
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| 15-8 | BankDirtyBits[7:0] | One per bank. Set when the currently open row has been written. |
| 15-8 | BankDirtyBits[7:0] | One per bank. Set when the currently open row has been written. Cleared when a new row is opened but not yet written to. |
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| 7-0 | BankValidBits[7:0] | One per bank. Set when a row is opened. Presumably only cleared by a refresh cycle. |
| 7-0 | BankValidBits[7:0] | One per bank. Set when a row is opened. Presumably only cleared by a refresh cycle. |
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}} |
}} |
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Writing any value this register will |
Writing any value to this register will set all valid bits to 0 and all dirty bits to 1. This causes the RI to become out-of-sync with RDRAM and will result in errors.<br> |
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Memory read/write requests to banks mapped above 8MiB do not update any of these bits. This may also cause out-of-sync errors as the RI appears to be unable to track the current open row state for banks above 8MiB. |
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'''Note:''' Some sources such as libultra's <code>rcp.h</code> header call this register <code>RI_WERROR</code>, however this register is unrelated to errors. The name <code>RI_BANK_STATUS</code> comes from a patent and is much more descriptive of the function of this register. |
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= Memory addressing = |
= Memory addressing = |
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