RDRAM Interface: Difference between revisions
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(RI_ERROR: Mention that even if the OverRange error is flagged it does not inhibit RDRAM packets from being sent out) |
(RI_CONFIG and RI_CURRENT_LOAD: Relate fields to relevant RAC signals, document read behavior for RI_CURRENT_LOAD) |
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<pre> |
<pre> |
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READ?/WRITE: |
READ?/WRITE: |
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[6] Enable/Disable automatic current calibration from controller. |
[6] Enable/Disable automatic current calibration from controller. Corresponds to the RAC CCtlEn input signal. |
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It selects whether |
It selects whether the value CC[5:0] will be written to current control register (AutoCC=0), or if an internally generated value should be used (AutoCC=1). |
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[5:0] Current Control Input. The value to be loaded into current control register when |
[5:0] Current Control Input. The value to be loaded into current control register when AutoCC is disabled. Corresponds to the RAC CCtlI input signal. |
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</pre> |
</pre> |
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<pre> |
<pre> |
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WRITE: |
WRITE: |
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Any write to this register causes a new value to be loaded into the RAC current control register. Corresponds to the RAC CCtlLd input signal. |
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The value loaded depends on the contents of the RI_CONFIG register, see there for details. |
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TOVERIFY: When AutoCC=1, a sufficient delay should be observed to let CC autocalibration stabilize. |
TOVERIFY: When AutoCC=1 in RI_CONFIG and this register is written, a sufficient delay should be observed to let CC autocalibration stabilize. |
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READ: |
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This register is intended to be write-only, the read behavior is unintended and returns a collection of bits from other registers: |
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[0] : RI_ERROR Ack |
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[1] : 1 TOVERIFY always 1? |
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[2] : 1 TOVERIFY always 1? |
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[3] : RI_MODE STOP_R |
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[4] : RI_SELECT TSEL[0] |
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[32:5] : 0 TOVERIFY always 0? |
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</pre> |
</pre> |
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