RDRAM Interface: Difference between revisions
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(RI_BANK_STATUS: Further details) |
(RI_ERROR: Mention that even if the OverRange error is flagged it does not inhibit RDRAM packets from being sent out) |
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Line 197: | Line 197: | ||
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| — || — || — || — || — || — || — || — |
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| colspan="8" | DirtyRefreshDelay [7:0] |
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{{#invoke:Register table|row|7:0}} |
{{#invoke:Register table|row|7:0}} |
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| U-? || U-? || U-? || U-? || U-? || R-? || R-? || R-? |
| U-? || U-? || U-? || U-? || U-? || R-? || R-? || R-? |
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Line 205: | Line 205: | ||
{{#invoke:Register table|definitions |
{{#invoke:Register table|definitions |
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| 31-3 | Undefined | Undefined |
| 31-3 | Undefined | Undefined |
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| 2 | Over | OverRangeError. Set when reading any addresses in the range <code>0x0080 0000</code> to <code>0x03EF FFFF</code>, even |
| 2 | Over | OverRangeError. Set when reading/writing any addresses in the range <code>0x0080 0000</code> to <code>0x03EF FFFF</code>, even if an RDRAM bank has been mapped there. However note that request packets are still sent out over the RDRAM bus even if this error was flagged. |
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| 1 | NAck | UnexpectedNAck. Set when RI sees an unexpected NAak (probably because bank status bits were wrong). |
| 1 | NAck | UnexpectedNAck. Set when RI sees an unexpected NAak (probably because bank status bits were wrong). |
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| 0 | Ack | MissingAck. Set when RI doesn't see an Ack (like when no RDRAM device was mapped to that address). <br> |
| 0 | Ack | MissingAck. Set when RI doesn't see an Ack (like when no RDRAM device was mapped to that address). <br> |