RDRAM Interface: Difference between revisions
Jump to navigation
Jump to search
Content added Content deleted
(Add RI_SELECT description) |
|||
| Line 118: | Line 118: | ||
| 31-8 | Undefined | Undefined |
| 31-8 | Undefined | Undefined |
||
| 7-4 | TSEL[3:0] | Configure transmit signals timings. Very likely related to RAC signals B{C,D,E}Sel. Usually set to <code>0x1</code>. |
| 7-4 | TSEL[3:0] | Configure transmit signals timings. Very likely related to RAC signals B{C,D,E}Sel. Usually set to <code>0x1</code>. |
||
| 3-0 | RSEL[3:0] | Configure receive signals timings. Very likely related to RAC |
| 3-0 | RSEL[3:0] | Configure receive signals timings. Very likely related to RAC signal RDSel. Usually set to <code>0x4</code>. |
||
}} |
}} |
||