RDRAM Interface: Difference between revisions
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(Verified the RI contains a RAC, and clarified which specific registers were defined on this page.) |
(Cleaned formatting and added content to RI_MODE register.) |
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W = Writable bit |
W = Writable bit |
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U = Undefined/Unused bit |
U = Undefined/Unused bit |
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-n = Default value n at |
-n = Default value n at boot |
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-? = Unknown default value |
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[x:y] = Specifies bits x to y, inclusively</pre> |
[x:y] = Specifies bits x to y, inclusively</pre> |
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==== <span style="display:none;">0x0470 0000 - RI_MODE ==== |
==== <span style="display:none;">0x0470 0000 - RI_MODE ==== |
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---- |
---- |
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{{#invoke:Register table|head| |
{{#invoke:Register table|head|600px|RI_MODE <code>0x0470 0000</code>}} |
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{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
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| U- |
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
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|- |
|- |
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| — || — || — || — || — || — || — || — |
| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|23:16}} |
{{#invoke:Register table|row|23:16}} |
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| U- |
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
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|- |
|- |
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| — || — || — || — || — || — || — || — |
| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|15:8}} |
{{#invoke:Register table|row|15:8}} |
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| U- |
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
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|- |
|- |
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| — || — || — || — || — || — || — || — |
| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|7:0}} |
{{#invoke:Register table|row|7:0}} |
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| U- |
| U-0 || U-0 || U-0 || U-0 || RW-1 || RW-1 || RW-? || RW-? |
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|- |
|- |
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| — || — || — || — || |
| — || — || — || — || STOP_R || STOP_T || colspan="2" | OP_MODE[1:0] |
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{{#invoke:Register table|foot}} |
{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
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<pre> |
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| 31-4 | Undefined | Initialized to <code>0</code> |
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READ/WRITE: |
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| 3 | STOP_R | Automatic halting of RAC clock used for receive logic when not in use, normally enabled. <br>1 {{=}} Enabled <br>0 {{=}} Disabled |
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[3] Enable/Disable controller Receive clock automatic stopping. |
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| 2 | STOP_T | Automatic halting of RAC clock used for transmit logic when not in use, normally enabled. <br>1 {{=}} Enabled <br>0 {{=}} Disabled |
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[2] Enable/Disable controller Transmit clock automatic stopping. |
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| 1-0 | OP_MODE[1:0] | Controls how Serial Mode (SMode) packets are sent to RDRAM modules. Usually set to <code>10</code>. <br>11 {{=}} Unknown <br>10 {{=}} Sends a packet before each RDRAM transaction. Tells the modules to enter standby mode after receiving each transaction. <br>01 {{=}} Sends a packet every 4 BusClk cycles. Tells the modules to always be active (consumes more power and usually not used). <br>00 {{=}} Sends continuous packets. After 272 BusClk cycles, all RDRAM modules will enter a reset mode. <br><i>Due to the timing differences, some changes will require a delay to become active.</i> |
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[1:0] Operating mode of RDRAM modules (not sure if it is the operating mode of the controller, if it makes the controller forward orders to place RDRAM modules in these states). |
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}} |
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0: Reset. place device in known state after poweron. |
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1: Active. device is active and ready to receive requests. This mode consumes the most power and is not used directly. |
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2: Standby. device automatically transition to this state after servicing a transaction. This is the default operating mode. |
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NOTE: some RDRAM datasheets mention a 4th mode PowerDown, but I'm not sure it is supported in N64 configuration. |
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NOTE: transition between these states takes several cycles, so after setting them some delay is necessary for them to be effective. |
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</pre> |
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==== <span style="display:none;">0x0470 0004 - RI_CONFIG ==== |
==== <span style="display:none;">0x0470 0004 - RI_CONFIG ==== |
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---- |
---- |
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{{#invoke:Register table|head| |
{{#invoke:Register table|head|600px|RI_CONFIG <code>0x0470 0004</code>}} |
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{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |