RDRAM Interface: Difference between revisions
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(Add details about refresh timings) |
(Fill in RI_ERROR and RI_BANK_STATUS) |
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==== <span style="display:none;">0x0470 0018 - RI_ERROR ==== |
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TODO: remaining registers |
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---- |
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{{#invoke:Register table|head|550px|RI_ERROR <code>0x0470 0018</code>}} |
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{{#invoke:Register table|row|31:24}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|23:16}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|15:8}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| colspan="8" | DirtyRefreshDelay [7:0] |
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{{#invoke:Register table|row|7:0}} |
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| U-? || U-? || U-? || U-? || U-? || R-? || R-? || R-? |
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|- |
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| — || — || — || — || — || OverRange || Ack ? || NAck ? |
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{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
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| 31-3 | Undefined | Undefined |
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| 2 | OverRange Error | Set when reading any addresses in the range <code>0x0080 0000</code> to <code>0x03EF FFFF</code>, even when an RDRAM bank has been mapped there. |
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| 1 | Ack Error? | ? |
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| 0 | NACK Error | Set when accessing an address with no mapped RDRAM device. This bit is set sometime during IPL3 init, presumably when probing memory size. |
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}} |
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Writing any value this register will clear any errors. |
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==== <span style="display:none;">0x0470 001c - RI_BANK_STATUS ==== |
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---- |
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{{#invoke:Register table|head|550px| RI_BANK_STATUS <code>0x0470 001c</code>}} |
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{{#invoke:Register table|row|31:24}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|23:16}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|15:8}} |
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| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-? |
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|- |
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| colspan="8" | BankDirtyBits[7:0] |
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{{#invoke:Register table|row|7:0}} |
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| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-? |
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|- |
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| colspan="8" | BankValidBits[7:0] |
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{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
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| 31-16 | ? | |
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| 15-8 | BankDirtyBits | One per bank. Set when a bank has been written since last refresh cycle |
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| 7-0 | BankValidBits | One per bank. Set when a bank has been read since last refresh cycle |
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}} |
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Writing any value this register will clear any tracking bits. |
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= Memory addressing = |
= Memory addressing = |