RDRAM Interface: Difference between revisions
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(Add RI_REFRESH description) |
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==== <span style="display:none;">0x0470 0010 - RI_REFRESH ==== |
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---- |
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{{#invoke:Register table|head|550px|RI_REFRESH <code>0x0470 0010</code>}} |
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{{#invoke:Register table|row|31:24}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|23:16}} |
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| U-? || U-? || U-? || RW-? || RW-? || RW-? || RW-? || RW-? |
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|- |
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| — || — || — || colspan="2" | MultiBank[??:0] || Opt || En || Bank |
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{{#invoke:Register table|row|15:8}} |
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| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? |
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|- |
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| colspan="8" | DirtyRefreshDelay [7:0] |
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{{#invoke:Register table|row|7:0}} |
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| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? |
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|- |
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| colspan="8" | CleanRefreshDelay [7:0] |
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{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
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| 31-?? | Undefined | Undefined |
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| ??-19| MultiBank[??:0] | Bitfield indicating multibanks rdram modules. (Bitfield size to be determined, very likely between 2 and 8). <br>Probably why RDRAM modules are re-ordered with multibanks modules first. |
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| 18 | Opt | Optimize. Usually set to <code>0x1</code>. |
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| 17 | En | Enable. Usually set to <code>0x1</code>. |
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| 16 | Bank | Usually set to <code>0x0</code>. |
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| 15-8 | DirtyRefreshDelay[7:0] | Usually set to <code>0x36</code>. |
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| 7-0 | CleanRefreshDelay[7:0] | Usually set to <code>0x34</code>. |
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}} |
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TODO: remaining registers |
TODO: remaining registers |