RDRAM: Difference between revisions
Update with new knowledge about MI's Upper mode
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!CPU Addr[9:0]!! Name !! Description
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See [[RDRAM Interface|RI page]] for more details about how
'''Reset and initialization:'''
* After RDRAM device reset, '''Delay''' needs to be set correctly before anything will work, see '''[[RDRAM#Reset Complications|Reset Complications]]'''
* After reset all devices will respond to Broadcast writes. Only the closet device in the Sin/Sout chain will respond to a non-broadcast write.
* Before the device will respond to Register reads, each device needs to be assigned a '''DeviceId''' and enabled by setting '''Mode's''' DeviceEnable bit.
* After each device has been enabled, the next device in the Sin/Sout chain will respond now respond to non-broadcast writes.
* Register reads will not return the correct value until the after the device's current control calibration as finished.
'''Endianness:'''
'''NOTE:''' In the following register description we will omit the ninth bit which is unused when accessing RDRAM registers, and describe them as a 32bit word instead of 4x{8,9}bit.▼
Rambus devices are little endian. Doesn't matter for regular memory, but that does mean registers are all byte swapped. The register descriptions below have been remapped to show big endian bit offsets.
'''Address alignment issues:'''
The Rambus register commands (Wreg, WregB and Rreg) are defined to be "Quadbyte" (32bit) transfers, and so expect the data to be in the first 4 bytes.But RI only supports transfers with 1 to 16 "Octbyte" (64 bits). This works fine for accessing registers with "even" addresses (when <code>Addr[2] == 0</code>), as the value is already mapped to the first 4 bytes of the read/write data packet. But when accessing "odd" registers (when<code>Addr[2] == 1</code>), the value ends up bytes 4-7 of the Octbyte transfer, which gets ignored.
''Note: Because RCP is big endian, it puts 32bit even addresses in the Upper half of the 64bit word, and 32bit odd addresses in the lower half, RI outputs the MSB first, so it ends up in byte 0 of the Rambus data packet.''
[[MIPS Interface#0x0430 0000 - MI MODE|MI MODE]]'s '''Upper mode''' is used work around this problem, as it forces MI to always map the value into the upper half of DBus, which results in the value always mapping to bytes 0-3 of the "Octbyte" transfer, while still passing the original address through. Nintendo's IPL3 compulsively warps all accesses to RDRAM register with writes to MI_MODE's SetUpper/ClearUpper. But you only actually need Upper Mode for accessing the "odd" registers.
▲'''NOTE:''' In the following register description we will omit the ninth bit which is unused when accessing RDRAM registers, and describe them as a 32bit word instead of 4x{8,9}bit.
==== <span style="display:none;">0x00 - DeviceType ====
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===== '''Reset Complications:''' =====
RI is hardwired to use a write delay of 1 TCycle, this means the Write request packet is send starting from (TCycle 0, RCP Cycle 0), finishing after 3 TCycles. 64bits of Data is send starting at (TCycle 4, RCP Cycle 1), finishing at (TCycle7, RCP Cycle 1.75)
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