RDRAM: Difference between revisions
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→RDRAM registers: warps -> wraps
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''Note: Because RCP is big endian, it puts 32bit even addresses in the Upper half of the 64bit word, and 32bit odd addresses in the lower half, RI outputs the MSB first, so it ends up in byte 0 of the Rambus data packet.''
[[MIPS Interface#0x0430 0000 - MI MODE|MI MODE]]'s '''Upper mode''' is used work around this problem, as it forces MI to always map the value into the upper half of DBus, which results in the value always mapping to bytes 0-3 of the "Octbyte" transfer, while still passing the original address through. Nintendo's IPL3 compulsively
'''NOTE:''' In the following register description we will omit the ninth bit which is unused when accessing RDRAM registers, and describe them as a 32bit word instead of 4x{8,9}bit.
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