Peripheral Interface: Difference between revisions
Updated length register behaviors
(Fixed directionality for DMA reads/writes) |
(Updated length register behaviors) |
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Line 88:
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | DRAM_ADDR[23:0] |
}}
'''Extra Details:'''
Line 114:
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-0 | CART_ADDR[31:0] |
}}
Line 139:
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | RD_LEN[23:0] | Number of bytes, minus one, to be transferred from RDRAM, to the PI bus
}}
'''Extra Details:'''
: Writing to this register will start the DMA transfer. Reading appears to always return `0x7F` (more research required).
==== <span style="display:none;">0x0460 000C - PI_WR_LEN ====
Line 164 ⟶ 166:
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | WR_LEN[23:0] | Number of bytes, minus one, to be transferred from the PI bus, into RDRAM
}}
'''Extra Details:'''
: Writing to this register will start the DMA transfer. Reading appears to always return `0x7F` (more research required).
==== <span style="display:none;">0x0460 0010 - PI_STATUS ====
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