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Peripheral Interface: Difference between revisions

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Peripheral Interface (view source)

Revision as of 21:43, 17 November 2022

428 bytes added ,  1 year ago
Revised wording and formatting
VisualWikitext
(reformat PI registers)
(Revised wording and formatting)
Line 88:
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | DRAM_ADDR[23:0] | Start address in RDRAM for PI DMAs; lsbitbit-0 is always 0
}}
'''Extra Details:'''
 
: Note that DMA transfers are buggy if the three lsbitsDRAM_ADDR[2:0] are not all zero, see [[#Unaligned DMA transfer|below]].
 
==== <span style="display:none;">0x0460 0004 - PI_CART_ADDR ====
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{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-0 | CART_ADDR[31:0] | Start address in cartridge for PI DMAs; lsbitbit-0 is always 0
}}
 
Line 133:
| colspan="8" | RD_LEN[15:8]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || ???RW-0
|-
| colspan="8" | RD_LEN[7:0]
Line 139:
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | RD_LEN[23:0] | Number of bytes, -1minus one, to be transferred from cart; lsbit mustbit-0 alwaysshould be 1 (butor doeselse itunexpected exist?behavior whatmight goesoccur wrong if it(documentation/research isn't?needed)
}}
 
Line 158:
| colspan="8" | WR_LEN[15:8]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || ???RW-0
|-
| colspan="8" | WR_LEN[7:0]
Line 164:
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | WR_LEN[23:0] | Number of bytes, -1minus one, to be transferred to cart; lsbitbit-0 must alwaysshould be 1, and undocumentedor thingselse gounexpected wrongbehavior ifmight itoccur is(documentation/research notneeded)
}}
 
Line 214:
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | BSD_DOMn_LATLAT[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-8 | Undefined | Initialized to <code>0</code>
| 7-0 | PI_BSD_DOMn_LATLAT[7:0] | The "LATch" timevalue is the number of FSBRCP cycles, -1minus one, after the address has been sent (a falling edge of ALELALE_L) and before the first read or write may start (falling edge of /RD or /WR)
}}
'''Extra Details:'''
 
: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's LAT using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set LAT = 64 (meaning (64+1)*16 = 1040ns).
The default value for PI_BSD_DOM1_LAT is 0x40 meaning (0x40+1)·16 = 1040ns, copied by IPL2 from the cartridge header.
 
==== <span style="display:none;">0x0460 00n8 - PI_BSD_DOMn_PWD ====
Line 242:
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | BSD_DOMn_PWDPWD[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-8 | Undefined | Initialized to <code>0</code>
| 7-0 | PI_BSD_DOMn_PWDPWD[7:0] | The "Pulse WiDth" value is the number of FSBRCP cycles, -1minus one, the read/RD or write/WR signals are held low
}}
'''Extra Details:'''
 
: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's PWD using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set PWD = 18 (meaning (18+1)*16 = 304ns).
The default value for PI_BSD_DOM1_PWD is 0x12 meaning (0x12+1)·16 = 304ns, copied by IPL2 from the cartridge header.
 
==== <span style="display:none;">0x0460 00nC - PI_BSD_DOMn_PGS ====
Line 270:
| U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | BSD_DOMn_PGSPGS[3:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-4 | Undefined | Initialized to <code>0</code>
| 3-0 | PI_BSD_DOMn_PGSPGS[3:0] | The "PaGe Size" isvalue theconfigures numberhow ofmany bits,bytes -1,can ofbe automaticsequentially incrementingread/written behavioron supportedthe bybus before sending the cartridgenext base address (Size {{=}} 2^(PGS+2) hardware.bytes)
}}
'''Extra Details:'''
: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's PGS using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set PGS = 7 (meaning 2^(7+2) = 512 bytes).
 
Page Size only matters for DMA transfers; all direct accesses via the PI are only ever 32 bits wide.
The default value for PI_BSD_DOM1_PGS is 0x7, copied by IPL2 from the cartridge header. This means the PI assumes it can transfer at most 2⁽⁷⁺²) bytes before it must latch a new address. Note that the maximum number of transfers will only happen when the address's least significant bits are all 0.
 
PageThe Sizemaximum only matters fornumber DMAof transfers; allwill directonly accesshappen towhen the PIaddress's isleast onlysignificant everbits 32are bitsall wide0.
 
==== <span style="display:none;">0x0460 00n0 - PI_BSD_DOMn_RLS ====
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| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || colspan="2" | BSD_DOMn_RLSRLS[1:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-2 | Undefined | Initialized to <code>0</code>
| 1-0 | PI_BSD_DOMn_RLSRLS[7:0] | The "ReLeaSe" timevalue is the number of FSBRCP cycles, -1minus one, that the read/RD or write/WR signals mustare stayheld high beforebetween theeach next16-bits read or write or addressof cycledata
}}
'''Extra Details:'''
 
: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's RLS using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set RLS = 3 (meaning (3+1)*16 = 64ns).
The default value for PI_BSD_DOM1_RLS is 3, meaning (3+1)·16 = 64ns, copied by IPL2 from the cartridge header.
 
= Physical Bus Pinout =
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