Peripheral Interface: Difference between revisions

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* Direct I/O: part of the 32-bit PI address space is [[Memory map|memory mapped]] to the CPU address space. This means that when the CPU accesses one of these memory mapped addresses, the PI will perform a read or write on the bus. The mapped addresses are only those in the range <code>0x0500_0000 - 0x1FBF_FFFF</code> and <code>0x1FD0_0000 - 0x7FFF_FFFF</code>. Addresses outside of these ranges can only be accessed via DMA. Notice also that direct I/O accesses can only be done as 32-bit words (concatenating two consecutive 16-bit reads), see [[Memory map#Ranges 0x0500'0000 - 0x1FBF'FFFF and 0x1FD0'0000 - 0x7FFF'FFFF (PI external bus)]] for more information.
 
'''NOTE:''' it is easy to get confused with the different kind of addresses. Addresses mentioned here are '''PI bus addresses''', which is a 32-bit namespace by itself. Addresses in the CPU physical memory map are a different namespace. They can be confused because of the memory mapped address, soaddresses: accessing physical address '''0x0700_0000 in the CPU''' does map exactly to '''PI address 0x0700_0000''', but in general the two namespaces are technically separated. For instance, '''PI address 0x0000_1234''' is a valid PI address on the bus where a device could be attached, but reading from physical address '''0x0000_1234 on the CPU''' accesses RDRAM instead; in fact PI address 0x0000_1234 is not memory mapped, so the only way to access it is via DMA.
 
=== Domains ===