Peripheral Interface: Difference between revisions
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The Peripheral Interface (or '''PI''', or Parallel Interface) is one of multiple I/O interfaces in the RCP, which is used to communicate with [[Game Pak|game cartridges]] or other devices connected to either the cartridge port or expansion port on the bottom of the console. (e.g. 64DD)
Memory mapped registers are used to configure the Peripheral Interface and initiate DMA reads and writes. The base address for these registers is <code>0x0460 0000</code>, also known as PI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add <code>0xA000 0000</code> to the address. As an example, to directly write to the PI_DRAM_ADDR register, use address <code>0xA460 0000</code>.
= Registers =
'''Table Notation:'''
<pre>
R = Readable bit
W = Writable bit
U = Undefined/Unused bit
-n = Default value n at power on
[x:y] = Specifies bits x to y, inclusively</pre>
==== <span style="display:none;">0x0460 0000 - PI_DRAM_ADDR</code> ====
----
{{#invoke:Register table|head|550px|PI_DRAM_ADDR <code>0x0460 0000</code>}}
{{#invoke:Register table|row|31:24}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
| colspan="8" | DRAM_ADDR[23:16]
{{#invoke:Register table|row|15:8}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
| colspan="8" | DRAM_ADDR[15:8]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
| colspan="8" | DRAM_ADDR[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | DRAM_ADDR[23:0] | RDRAM address used in PI DMAs
}}
'''TODO'''
= Physical Bus Pinout =
The PI Bus is a Bi-directional and MUX'ed interface where there is a 16bit data path to the Rom, 64DD, Flash Ram and SRAM ram chips is used to send both the wanted address and data to and from the RCP. This is not to be confused with the serial EEPROM, CIC and RTC (real time clock) chips that go through the SI interface and PIF chip via the cartridge port as well.
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Reads or writes to these physical memory segments are mapped to the PI bus. For example, attempting to read from address 0x10000000 will cause a PI bus read at address 0x10000000. This means that even if a cartridge/device has data stored at addresses outside these segments, software running on the console will not be able to access it. Historically, each segment was intended for a different purpose. Game cartridges always expect software to read from the <code>0x10000000 - 0x1FBFFFFF</code> segment in order to access the game's ROM data. Custom hardware and software could potentially utilize any or all of these segments in different/unintended ways. Some flashcarts are known to use <code>0x1FD00000 - 0x7FFFFFFF</code> for special features or debugging.
{| class="wikitable"
! colspan=2 | Address Range !! Name !! Original Intended Usage
▲|+
|-
| 0x05000000 || 0x05FFFFFF || Domain 2, Address 1 || N64DD control registers
▲|2
|-
| 0x06000000 || 0x07FFFFFF || Domain 1, Address 1 || N64DD IPL ROM
▲|1
|-
| 0x08000000 || 0x0FFFFFFF || Domain 2, Address 2 || Cartridge SRAM
▲|2
|-
| 0x10000000 || 0x1FBFFFFF || Domain 1, Address 2 || Cartridge ROM
|-
| 0x1FD00000 || 0x7FFFFFFF || Domain 1, Address 3 || Unknown
|}
0x0460 0000 to 0x046F FFFF Address range:
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An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit (2Byte) value as will transfer from that offset to RDRAM.
The PI_RD_LEN_REG and PI_WR_LEN_REG can be any length, as long as it is a 2 byte aligned amount (more testing is to be done on this to confirm this)
An un-aligned ROM dma transfer is when you use the PI_DRAM_ADDR_REG and not set it as a 8 Byte aligned address and use variable PI_RD_LEN_REG and PI_WR_LEN_REG lengths.
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