Peripheral Interface

Parallel Interface Registers

0x0460 0000 to 0x046F FFFF  Address range:

Reg Name	Reg Address (32Bit)	Read or Write	Discription
PI_DRAM_ADDR_REG [23:0]	32'h0460_0000	R/W	This is the starting address in RDRAM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address
PI_CART_ADDR_REG [31:0]	32'h0460_0004	R/W	This is the starting address in ROM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address
PI_RD_LEN_REG [23:0]	32'h0460_0008	R/W	The is the amount of bytes to be transferred from RDRAM to the ROM location (this has to be a value in a multiple of 16bits (2 Bytes))
PI_WR_LEN_REG [23:0]	32'h0460_000C	R/W	The is the amount of bytes to be transferred from ROM to the RDRAM location (this can be byte amount)
PI_STATUS_REG	32'h0460_0010	R/W	On Read: Bit [0] : DMA is busy Bit [1] : IO Busy Bit [2] : DMA Error Bit [3] : Interrupt (DMA Completed) On Write: Bit [0] : Reset the DMA controller and stop any transfer begin done Bit [1] : Clear Interrupt
PI_BSD_DOM1_LAT_REG PI_BSD_DOM2_LAT_REG [7:0]	32'h0460_0014 32'h0460_0024	R/W	This is a 8 bit counter for the timing between sending the address to the ROM and when to read or write the block of data over the cart bus This counter runs after the Low Address is asserted on the bus and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the bus can then start the Read or write process. Then the PI_BSD_DOMX_RLS_REG process starts for the data transfer Default value set by games is (8'h40)
PI_BSD_DOM1_PWD_REG PI_BSD_DOM2_PWD_REG [7:0]	32'h0460_0018 32'h0460_0028	R/W	This is a 8 bit counter for the timing on how long the Read or Write signal is to stay LOW before it can go HIGH This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to idle or back to PI_BSD_DOM1_RLS_REG. Default value set by games is (8'h12)
PI_BSD_DOM1_PGS_REG PI_BSD_DOM2_PGS_REG [7:0]	32'h0460_001C 32'h0460_002C	R/W
PI_BSD_DOM1_RLS_REG PI_BSD_DOM2_RLS_REG [7:0]	32'h0460_0020 32'h0460_0030	R/W

Aligned DMA Transfer

An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit value