Peripheral Interface: Difference between revisions

==== <span style="display:none;">0x0460 0040 - PI_BB_ATB_UPPER</code> ====

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{{#invoke:Register table|head|800px|PI_BB_ATB_UPPER <code>0x0460 0040</code> (Read)}}

{{#invoke:Register table|row|31:24}}

| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?

|-

| — || — || — || — || — || — || — || —

{{#invoke:Register table|row|23:16}}

| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?

|-

| — || — || — || — || — || — || — || —

{{#invoke:Register table|row|15:8}}

| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?

|-

| — || — || — || — || — || — || — || IV Source

{{#invoke:Register table|row|7:0}}

| U-? || U-? || U-? || U-? || colspan="4"| U-?

|-

| — || — || — || — || colspan="4"| log2(Num Blocks)

{{#invoke:Register table|foot}}

{{#invoke:Register table|definitions

| 8 | IV Source | Where to source the Initialization Vector from for AES decryption. See below.

| 5 | ? | Unknown. System software sets this to 1.

| 4 | ? | Unknown. System software sets this to 1.

| 3-0 | log2(Num Blocks) | log2 of the number of contiguous NAND blocks to map (-1). This is applied to an ATB entry when '''ATB_LOWER''' registers are written.

}}

'''Extra Details'''

: This register supplies only half of the configuration for an ATB entry, also see the '''PI_BB_ATB_LOWER''' array of registers where PI addresses and the starting NAND block number are specified.

: ATB is the N64 PI address space emulator that translates PI DMAs into NAND flash accesses. Data stored on the NAND is encrypted with AES, ATB must transparently decrypt the data when a PI DMA requests it. To decrypt AES at an 0x10-aligned position '''P''' the data at '''P-0x10''' is also required, or if '''P=0''' then the Initialization Vector (IV) is required. At the start of a DMA, ATB will try to find the entry that maps the PI address for '''P-0x10''' into the NAND to fetch the needed prior data; for all cases but '''P=0''' this should resolve correctly with a contiguous PI address space mapping. To handle the '''P=0''' case an additional dummy mapping must precede the base address of the desired mapping, with the IV Source bit set to 1. When the IV Source bit is 1 the IV will be pulled from the memory at '''0x046104D0''' rather than reading any data off the NAND. For example if the mapping begins at PI address 0x10000000 as for Cartridge ROM, a dummy mapping for PI address 0x0FFFC000 with IV Source set to 1 should be programmed.

==== <span style="display:none;">0x0461 0500 to 0x0461 0800 - PI_BB_ATB_LOWER</code> ====

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{{#invoke:Register table|head|800px|PI_BB_ATB_LOWER <code>0x0461 0500 - 0x0461 0800</code>}}

{{#invoke:Register table|row|31:24}}

| colspan="8"| U-?

|-

| colspan="8"| NAND Block Number [15:8]

{{#invoke:Register table|row|23:16}}

| colspan="8"| U-?

|-

| colspan="8"| NAND Block Number [7:0]

{{#invoke:Register table|row|15:8}}

| colspan="8"| U-?

|-

| colspan="8"| PI Physical Address [29:14] [15:8]

{{#invoke:Register table|row|7:0}}

| colspan="8"| U-?

|-

| colspan="8"| PI Physical Address [29:14] [7:0]

{{#invoke:Register table|foot}}

{{#invoke:Register table|definitions

| 31-16 | NAND Block Number | Starting block number to map to the provided PI address.

| 15-0 | PI Physical Address [29:14] | PI address to begin the mapping at, divided by 0x4000 the NAND block size.

}}

'''Extra Details'''

: There are 192 '''ATB_LOWER''' registers. Issuing a write to a particular register will program that ATB entry with a mapping, also using the current contents of '''ATB_UPPER''' to complete the entry configuration.

: The number of blocks to map comes from '''ATB_UPPER'''.

: Mappings involving non-contiguous or unsorted NAND blocks must occupy multiple ATB entries.

: These ATB entries should be sorted by PI address, from lowest to highest.

: It is not possible to write addresses that are not aligned to the NAND block size (0x4000)

: It is not possible to map more contiguous blocks than the PI address alignment allows in a single entry. For example it is not possible to map 2 contiguous blocks in the same ATB entry if the base address is 0x10004000. The maximum number of blocks you can map for given <code>(pi_addr, nblocks)</code> in a single ATB entry is <code>1 << min(ctz(pi_addr/0x4000), ceil(log2(nblocks)))</code> where <code>ctz(x)</code> counts the number of trailing zeros in the binary representation of <code>x</code>.