Peripheral Interface: Difference between revisions

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{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | DRAM_ADDR[23:0] | Start address in RDRAM for PI DMAs; lsbit is always 0
| 23-0 | DRAM_ADDR[23:0] | Start address in RDRAM for PI DMAs; bit-0 is always 0
}}
}}
'''Extra Details:'''

Note that DMA transfers are buggy if the three lsbits are not all zero, see [[#Unaligned DMA transfer|below]].
: Note that DMA transfers are buggy if DRAM_ADDR[2:0] are not all zero, see [[#Unaligned DMA transfer|below]].


==== <span style="display:none;">0x0460 0004 - PI_CART_ADDR ====
==== <span style="display:none;">0x0460 0004 - PI_CART_ADDR ====
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{{#invoke:Register table|foot}}
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-0 | CART_ADDR[31:0] | Start address in cartridge for PI DMAs; lsbit is always 0
| 31-0 | CART_ADDR[31:0] | Start address in cartridge for PI DMAs; bit-0 is always 0
}}
}}


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| colspan="8" | RD_LEN[15:8]
| colspan="8" | RD_LEN[15:8]
{{#invoke:Register table|row|7:0}}
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || ???
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
|-
| colspan="8" | RD_LEN[7:0]
| colspan="8" | RD_LEN[7:0]
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{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | RD_LEN[23:0] | Number of bytes, -1, to be transferred from cart; lsbit must always be 1 (but does it exist? what goes wrong if it isn't?)
| 23-0 | RD_LEN[23:0] | Number of bytes, minus one, to be transferred from cart; bit-0 should be 1 or else unexpected behavior might occur (documentation/research needed)
}}
}}


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| colspan="8" | WR_LEN[15:8]
| colspan="8" | WR_LEN[15:8]
{{#invoke:Register table|row|7:0}}
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || ???
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
|-
| colspan="8" | WR_LEN[7:0]
| colspan="8" | WR_LEN[7:0]
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{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | WR_LEN[23:0] | Number of bytes, -1, to be transferred to cart; lsbit must always be 1, and undocumented things go wrong if it is not
| 23-0 | WR_LEN[23:0] | Number of bytes, minus one, to be transferred to cart; bit-0 should be 1 or else unexpected behavior might occur (documentation/research needed)
}}
}}


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| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
|-
| colspan="8" | BSD_DOMn_LAT[7:0]
| colspan="8" | LAT[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-8 | Undefined | Initialized to <code>0</code>
| 31-8 | Undefined | Initialized to <code>0</code>
| 7-0 | PI_BSD_DOMn_LAT[7:0] | The "LATch" time is the number of FSB cycles, -1, after the address has been sent (a falling edge of ALEL) before the first read or write may start
| 7-0 | LAT[7:0] | The "LATch" value is the number of RCP cycles, minus one, after the address has been sent (falling edge of ALE_L) and before the first read or write may start (falling edge of /RD or /WR)
}}
}}
'''Extra Details:'''

: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's LAT using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set LAT = 64 (meaning (64+1)*16 = 1040ns).
The default value for PI_BSD_DOM1_LAT is 0x40 meaning (0x40+1)·16 = 1040ns, copied by IPL2 from the cartridge header.


==== <span style="display:none;">0x0460 00n8 - PI_BSD_DOMn_PWD ====
==== <span style="display:none;">0x0460 00n8 - PI_BSD_DOMn_PWD ====
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| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
|-
| colspan="8" | BSD_DOMn_PWD[7:0]
| colspan="8" | PWD[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-8 | Undefined | Initialized to <code>0</code>
| 31-8 | Undefined | Initialized to <code>0</code>
| 7-0 | PI_BSD_DOMn_PWD[7:0] | The "Pulse WiDth" is the number of FSB cycles, -1, the read or write signals are held low
| 7-0 | PWD[7:0] | The "Pulse WiDth" value is the number of RCP cycles, minus one, the /RD or /WR signals are held low
}}
}}
'''Extra Details:'''

: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's PWD using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set PWD = 18 (meaning (18+1)*16 = 304ns).
The default value for PI_BSD_DOM1_PWD is 0x12 meaning (0x12+1)·16 = 304ns, copied by IPL2 from the cartridge header.


==== <span style="display:none;">0x0460 00nC - PI_BSD_DOMn_PGS ====
==== <span style="display:none;">0x0460 00nC - PI_BSD_DOMn_PGS ====
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| U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0
| U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0
|-
|-
| — || — || — || — || colspan="4" | BSD_DOMn_PGS[3:0]
| — || — || — || — || colspan="4" | PGS[3:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-4 | Undefined | Initialized to <code>0</code>
| 31-4 | Undefined | Initialized to <code>0</code>
| 3-0 | PI_BSD_DOMn_PGS[3:0] | The "PaGe Size" is the number of bits, -1, of automatic incrementing behavior supported by the cartridge hardware.
| 3-0 | PGS[3:0] | The "PaGe Size" value configures how many bytes can be sequentially read/written on the bus before sending the next base address (Size {{=}} 2^(PGS+2) bytes)
}}
}}
'''Extra Details:'''
: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's PGS using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set PGS = 7 (meaning 2^(7+2) = 512 bytes).


Page Size only matters for DMA transfers; all direct accesses via the PI are only ever 32 bits wide.
The default value for PI_BSD_DOM1_PGS is 0x7, copied by IPL2 from the cartridge header. This means the PI assumes it can transfer at most 2⁽⁷⁺²) bytes before it must latch a new address. Note that the maximum number of transfers will only happen when the address's least significant bits are all 0.


Page Size only matters for DMA transfers; all direct access to the PI is only ever 32 bits wide.
The maximum number of transfers will only happen when the address's least significant bits are all 0.


==== <span style="display:none;">0x0460 00n0 - PI_BSD_DOMn_RLS ====
==== <span style="display:none;">0x0460 00n0 - PI_BSD_DOMn_RLS ====
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| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
|-
| — || — || — || — || — || — || colspan="2" | BSD_DOMn_RLS[1:0]
| — || — || — || — || — || — || colspan="2" | RLS[1:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-2 | Undefined | Initialized to <code>0</code>
| 31-2 | Undefined | Initialized to <code>0</code>
| 1-0 | PI_BSD_DOMn_RLS[7:0] | The "ReLeaSe" time is the number of FSB cycles, -1, the read or write signals must stay high before the next read or write or address cycle
| 1-0 | RLS[7:0] | The "ReLeaSe" value is the number of RCP cycles, minus one, that the /RD or /WR signals are held high between each 16-bits of data
}}
}}
'''Extra Details:'''

: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's RLS using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set RLS = 3 (meaning (3+1)*16 = 64ns).
The default value for PI_BSD_DOM1_RLS is 3, meaning (3+1)·16 = 64ns, copied by IPL2 from the cartridge header.


= Physical Bus Pinout =
= Physical Bus Pinout =
Retrieved from "https://n64brew.dev/wiki/Peripheral_Interface"