Peripheral Interface: Difference between revisions
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Mazamars312 (talk | contribs) (Domains data changed) |
Mazamars312 (talk | contribs) (Updated images and up to aligned DMA transfers) |
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=== PI Interface Process === |
=== PI Interface Process === |
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Address output: |
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[[File:Rom address output.png|border|left|frameless|984x984px|Rom Address Output]] |
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Data Read: |
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[[File:Rom Read Data.png|alt=Rom Read Data|border|left|frameless|1003x1003px|Rom Read Data]] |
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Constant Read: |
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[[File:Constant ROM Access.png|border|left|frameless|1522x1522px|Constant ROM Access]] |
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=== Aligned DMA Transfer === |
=== Aligned DMA Transfer === |
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An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit value |
An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit (2Byte) value as will transfer from that offset to RDRAM (more to come) |
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