Peripheral Interface: Difference between revisions
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| U-? || U-? || U-? || U-? || colspan="4"| U-? |
| U-? || U-? || U-? || U-? || colspan="4"| U-? |
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| — || — || |
| — || — || CpuEn || DmaEn || colspan="4"| log2(Num Blocks) |
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{{#invoke:Register table|foot}} |
{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
{{#invoke:Register table|definitions |
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| 8 | IV Source | Where to source the Initialization Vector from for AES decryption. See below. |
| 8 | IV Source | Where to source the Initialization Vector from for AES decryption. See below. |
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| 5 | CpuEn | If set to 1, the mapping will be enabled for CPU reads |
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| 5 | ? | Unknown. System software sets this to 1. |
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| 4 | DmaEn | If set to 1, the mapping will be enabled for DMA reads |
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| 4 | ? | Unknown. System software sets this to 1. |
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| 3-0 | log2(Num Blocks) | log2 of the number of contiguous NAND blocks to map. This is applied to an ATB entry when '''ATB_LOWER''' registers are written. |
| 3-0 | log2(Num Blocks) | log2 of the number of contiguous NAND blocks to map. This is applied to an ATB entry when '''ATB_LOWER''' registers are written. |
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}} |
}} |