Peripheral Interface: Difference between revisions
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Mazamars312 (talk | contribs) (Start of this page) |
Mazamars312 (talk | contribs) (Some PI data) |
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!Discription |
!Discription |
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|PI_DRAM_ADDR_REG |
|PI_DRAM_ADDR_REG [23:0] |
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|32'h0460_0000 |
|32'h0460_0000 |
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|R/W |
|R/W |
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|This is the starting address in RDRAM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address |
|This is the starting address in RDRAM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address |
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|PI_CART_ADDR_REG |
|PI_CART_ADDR_REG [31:0] |
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|32'h0460_0004 |
|32'h0460_0004 |
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|R/W |
|R/W |
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|This is the starting address in ROM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address |
|This is the starting address in ROM that the PI DMA is to read or write from. This is a 16bit (2Byte) Aligned address |
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|PI_RD_LEN_REG |
|PI_RD_LEN_REG [23:0] |
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|32'h0460_0008 |
|32'h0460_0008 |
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|R/W |
|R/W |
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|The is the amount of bytes to be transferred from RDRAM to the ROM location (this has to be a value in a multiple of 16bits (2 Bytes)) |
|The is the amount of bytes to be transferred from RDRAM to the ROM location (this has to be a value in a multiple of 16bits (2 Bytes)) |
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|PI_WR_LEN_REG |
|PI_WR_LEN_REG [23:0] |
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|32'h0460_000C |
|32'h0460_000C |
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|R/W |
|R/W |
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|PI_BSD_DOM1_LAT_REG |
|PI_BSD_DOM1_LAT_REG |
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PI_BSD_DOM2_LAT_REG |
PI_BSD_DOM2_LAT_REG [7:0] |
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|32'h0460_0014 |
|32'h0460_0014 |
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|PI_BSD_DOM1_PWD_REG |
|PI_BSD_DOM1_PWD_REG |
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PI_BSD_DOM2_PWD_REG |
PI_BSD_DOM2_PWD_REG |
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[7:0] |
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|32'h0460_0018 |
|32'h0460_0018 |
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32'h0460_0028 |
32'h0460_0028 |
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|PI_BSD_DOM1_PGS_REG |
|PI_BSD_DOM1_PGS_REG |
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PI_BSD_DOM2_PGS_REG |
PI_BSD_DOM2_PGS_REG |
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[7:0] |
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|32'h0460_001C |
|32'h0460_001C |
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32'h0460_002C |
32'h0460_002C |
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|PI_BSD_DOM1_RLS_REG |
|PI_BSD_DOM1_RLS_REG |
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PI_BSD_DOM2_RLS_REG |
PI_BSD_DOM2_RLS_REG |
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[7:0] |
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|32'h0460_0020 |
|32'h0460_0020 |
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32'h0460_0030 |
32'h0460_0030 |
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=== PI Interface Process === |
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=== Aligned DMA Transfer === |
=== Aligned DMA Transfer === |
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An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address |
An aligned DMA transfer is when the PI_DRAM_ADDR_REG is set to a 64bit (8byte) aligned address. The PI_CART_ADDR_REG can be any 16bit value |
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