Peripheral Interface: Difference between revisions
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(PI_BB_NAND_CTRL, PI_BB_NAND_ADDR) |
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'''Extra Details:''' |
'''Extra Details:''' |
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: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's RLS using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set RLS = 3 (meaning (3+1)*16 = 64ns). |
: During [[Initial_Program_Load#IPL2|IPL2]], the N64 will initialize Domain 1's RLS using data read from the cartridge [[ROM_Header|ROM header]]. All official ROMs set RLS = 3 (meaning (3+1)*16 = 64ns). |
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= iQue Player-specific registers = |
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'''Table Notation:''' |
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<pre> |
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R = Readable bit |
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W = Writable bit |
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U = Undefined/Unused bit |
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-n = Default value n at power on |
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[x:y] = Specifies bits x to y, inclusively</pre> |
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==== <span style="display:none;">0x0460 0048 - PI_BB_NAND_CTRL</code> ==== |
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---- |
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{{#invoke:Register table|head|800px|PI_BB_NAND_CTRL <code>0x0460 0048</code> (Read)}} |
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{{#invoke:Register table|row|31:24}} |
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| R-0 || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| Busy || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|23:16}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|15:8}} |
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| U-? || U-? || U-? || U-? || U-? || R-0 || U-? || U-? |
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|- |
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| — || — || — || — || — || Error || — || — |
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{{#invoke:Register table|row|7:0}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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|- |
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| — || — || — || — || — || — || — || — |
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{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
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| 31 | Busy | Indicates that a command is currently executing. |
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| 10 | Error | Indicates some sort of error occurred. Exact meaning is unknown. |
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}} |
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{{#invoke:Register table|head|800px|PI_BB_NAND_CTRL <code>0x0460 0048</code> (Write)}} |
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{{#invoke:Register table|row|31:24}} |
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| W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0 || W-0 |
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|- |
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| Execute || Interrupt || — || — || — || — || — || — |
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{{#invoke:Register table|row|23:16}} |
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| colspan="8"| W-0 |
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|- |
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| colspan="8"| NAND Command |
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{{#invoke:Register table|row|15:8}} |
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| W-0 || W-0 || colspan="2"| W-0 || W-0 || W-0 || colspan="2" | W-0 |
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|- |
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| — || Buffer Select || colspan="2"| Device Select || Do ECC || Multicycle || colspan="2"| Data Length [9:8] |
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{{#invoke:Register table|row|7:0}} |
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| colspan="8"| W-0 |
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|- |
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| colspan="8"| Data Length [7:0] |
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{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
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| 31 | Execute | Setting this bit when writing will cause the last written command to begin execution. |
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| 30 | Interrupt | Whether the FLASH interrupt should be raised when the command finishes execution. |
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| 29 | ? | Unknown. Set when issuing Page Program (first cycle) |
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| 28 | ? | Unknown. Set when issuing Read 1, Read Status and Read ID |
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| 27 | ? | Unknown. Set when issuing Read 1, Block Erase (first cycle) and Page Program (first cycle) |
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| 26 | ? | Unknown. Set when issuing Read 1, Block Erase (first cycle) and Page Program (first cycle) |
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| 25 | ? | Unknown. Set when issuing Read 1, Block Erase (first cycle) and Page Program (first cycle) |
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| 24 | ? | Unknown. Set when issuing Read 1, Read ID and Page Program (first cycle) |
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| 23-16 | NAND Command | NAND Command to execute. Corresponds directly to commands for the K9F1208U0M flash. |
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| 15 | ? | Unknown. Set when issuing Read 1, Block Erase (second cycle) and Page Program (second cycle) |
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| 14 | Buffer Select | Selects which half of the 0x400-byte PI Buffer mapped at PI+0x10000 should be used for DMA operations. |
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| 13-12 | Device Select | Corresponds to Chip Enable signals on the card connector. Typically 0. |
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| 11 | Do ECC | Whether to do ECC |
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| 10 | Multicycle | Set to 1 if the command issued was not the last command in a multi-cycle sequence. |
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| 9-0 | Data Length | Data transfer length in bytes. Unlike most other lengths this is not length minus one, a length of 0 can be specified. |
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}} |
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'''Extra Details:''' |
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: Writing 0 to this register will clear any pending FLASH interrupt. |
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==== <span style="display:none;">0x0460 0070 - PI_BB_NAND_ADDR</code> ==== |
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---- |
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{{#invoke:Register table|head|800px|PI_BB_NAND_ADDR <code>0x0460 0070</code>}} |
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{{#invoke:Register table|row|31:24}} |
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| colspan="5"| U-? || colspan="3"| W-? |
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|- |
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| colspan="5"| — || colspan="3"| Address [26:24] |
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{{#invoke:Register table|row|23:16}} |
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| colspan="8"| W-? |
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|- |
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| colspan="8"| Address [23:16] |
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{{#invoke:Register table|row|15:8}} |
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| colspan="8"| W-? |
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|- |
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| colspan="8"| Address [15:8] |
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{{#invoke:Register table|row|7:0}} |
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| colspan="8"| W-? |
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|- |
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| colspan="8"| Address [7:0] |
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{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
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| ?-0 | Address | Set the NAND flash address that commands issued by '''PI_BB_NAND_CTRL''' will target. Exact bit width is unknown, however it is at least enough to address 128MiB (27 bits) |
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}} |
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'''Extra Details:''' |
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: To convert a page number to an address, multiply it by 512. |
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: To convert a block number to an address, multiply it by 0x4000. |
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= Physical Bus Pinout = |
= Physical Bus Pinout = |